Nondestructive Read Circuit for Memristor-Based Memories
01 Jan 2018-pp 123-131
TL;DR: A nondestructive read circuit which does not require an AC bias scheme and uses memristor as a feedback element in the noninverting operational amplifier to improve the speed of the memory access and reduces the power dissipated.
Abstract: Background: Memristor is a two-terminal passive nanodevice whose resistance (conductance) is a function of the past current flow. It is nonvolatile in nature and stores the binary data in the form of resistance. Its compatibility with the existing CMOS memory peripherals makes it interesting in the field of memory design. High density memories are realizable with the use of multilevel crossbar array of memristors. To write data into the memristor are as simple as to apply a DC bias. But reading in a similar trend would yield the loss of data. Various solutions based on AC bias, etc., have been proposed earlier. Methods/Statistical analysis: This paper explains a nondestructive read circuit which does not require an AC bias scheme. The proposed technique uses memristor as a feedback element in the noninverting operational amplifier. Hence, the resistance of the element is not much affected due to read operation. This makes the circuit more stable and nondestructive read operation. Findings: As the proposed circuit reads the content of the memristor memory without disturbing the content of the cell, it avoids refreshing or restoration of the memristor content after each read operation. By that, it improves the speed of the memory access and reduces the power dissipated. Application/Improvements: As the memristor memories support multilevel data storage, the proposed circuit can be modified to perform nondestructive read the content of multilevel memristor memories.
Citations
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01 Jan 2021
TL;DR: A new crossbar architecture that is capable of storing multibit per cell and eliminates the sneak paths without adding any complex circuitry is introduced and simulation results prove that the proposed circuitry can read the memory content even after 2000 cycles without any sneak paths problem.
Abstract: The memristor, the fourth fundamental elements have shown the potential to revolutionize the present storage, analog, and digital computational technologies. The ability to remember its pr...
2 citations
30 Dec 2022
TL;DR: In this article , the authors used the VTEAM model to describe the simulated memristor and analyzed the power, latency, and transistor count of the proposed CMOS-based hybrid memristors-based combinational circuits.
Abstract: Recently, extending the use of memristor technology from memory to computing has received a lot of attention. Memristor-based logic design is a new concept that aims to make computing systems more efficient. Several logic families have emerged, each with its own set of characteristics. In this paper, CMOS-based hybrid memristor-based combinational circuits are designed. Many computational devices require combinational circuits. All of the proposed designs were analysed for power, latency, and transistor count. Cadence Virtuoso is used for simulation of circuits. In this study, we used the VTEAM model to describe the simulated memristor because it is easy to understand and gives accurate results.
1 citations
TL;DR: In this article , the authors used the VTEAM model to describe the simulated memristor and analyzed the power, latency, and transistor count of the proposed CMOS-based hybrid MEMR-based combinational circuits.
Abstract: ░ ABSTRACT - Recently, extending the use of memristor technology from memory to computing has received a lot of attention. Memristor-based logic design is a new concept that aims to make computing systems more efficient. Several logic families have emerged, each with its own set of characteristics. In this paper, CMOS-based hybrid memristor-based combinational circuits are designed. Many computational devices require combinational circuits. All of the proposed designs were analysed for power, latency, and transistor count. Cadence Virtuoso is used for simulation of circuits. In this study, we used the VTEAM model to describe the simulated memristor because it is easy to understand and gives accurate results.
1 citations
References
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TL;DR: By starting from basicmemristor device equations, a comprehensive set of properties and design equations for memristor based memories are developed, specifically targeting key electrical memristOr device characteristics relevant to memory operations.
Abstract: Novel nonvolatile universal memory technology is essential for providing required storage for nanocomputing. As a potential contender for the next-generation memory, the recently found "the missing fourth circuit element," memristor, has drawn a great deal of research interests. In this paper, by starting from basic memristor device equations, we develop a comprehensive set of properties and design equations for memristor based memories. Our analyses are specifically targeting key electrical memristor device characteristics relevant to memory operations. Using our derived properties, we investigate the design of read and write circuits and analyze important data integrity and noise-tolerance is sues.
294 citations
TL;DR: The fault analysis reveals that unique faults occur in addition to some conventional memory faults, and the detection of such unique faults cannot be guaranteed with just the application of traditional march tests, so a new Design-for-Testability (DfT) concept is presented to facilitate the Detection of the unique faults.
Abstract: Memristor-based memory technology, also referred to as resistive RAM (RRAM), is one of the emerging memory technologies potentially to replace conventional semiconductor memories such as SRAM, DRAM, and flash. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques, and reliability improvement. However, research on (manufacturing) test for yield and quality improvement is still in its infancy stage. This paper presents fault analysis and modeling for open defects based on electrical simulation, introduces fault models, and proposes test approaches for RRAMs. The fault analysis reveals that unique faults occur in addition to some conventional memory faults, and the detection of such unique faults cannot be guaranteed with just the application of traditional march tests. The paper also presents a new Design-for-Testability (DfT) concept to facilitate the detection of the unique faults. Two DfT schemes are developed by exploiting the access time duration and supply voltage level of the RRAM cells, and their simulation results show that the fault coverage can be increased with minor circuit modification. As the fault behavior may vary due to process variations, the DfT schemes are extended to be programmable to track the changes and further improve the fault/defect coverage.
97 citations
TL;DR: The proposed Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers forms the base of area and power efficient testing methodologies for digital circuits.
Abstract: Background: Current technologies results in gradual increase in sensitiveness towards faults causing malfunctioning of the circuit. This paper presents the novel design of Built-In-Self-Test (BIST) using self-checking circuits for bit array multipliers. Methods: The design of BIST comprises of self-checking full adder which ensures fault detection on the same chip area. Each regular full adders and half adders in bit array multipliers are replaced by self-checking full adder so that any transient or permanent faults can be detected and recovered. The proposed BIST design also allows power saving procedures in Power Efficient-Test Pattern Generator (PE-TPG). Findings: Simulation results shows that implementation of this self-checking full adder into standard bit array multiplier minimizes the area overhead and power consumption by 25%-30% as compared to previous self-checking designs. The proposed BIST can handle up to ten faults with 70% probability of error detection, which is higher than earlier Double Modular Redundancy (DMR) as well as Triple Modular Redundancy (TMR) technique with handling of six faults with 60% error detection probability. Conclusion: The proposed BIST design forms the base of area and power efficient testing methodologies for digital circuits. The architecture of BIST can be modified according to the data path of multiplier under test.
11 citations
19 Apr 2014
TL;DR: A new Read/Write circuit design is proposed based on the Memristor as a memory element that exhibits low power consumption, short delay time, and occupying less layout area.
Abstract: The recently found Memristor is a potential candidate for the next-generation memory because of its nano-scale and non-volatile advantages. In this paper, a new Read/Write circuit design is proposed based on the Memristor as a memory element. The proposed circuit exhibits low power consumption, short delay time, and occupying less layout area. In addition, the proposed circuit has the advantage of non-destructive successive reading cycles capability.
9 citations
TL;DR: This proposed scheme becomes more efficient by using cellular automata as test pattern generation and response analyzer using rule 90 to test the circuit under test in online mode with less concurrent test latency and less area overhead.
Abstract: Background/objectives: Built in Self Test Architectures are used for the online or offline testing of the digital circuits and can be operated both in normal as well as test mode. So the objective is to test the circuit under test in online mode with less concurrent test latency and less area overhead. Methods/ Statistical Analysis: In the case of normal mode the time required for testing becomes undesirable parameter so here we prefer offline testing method with concurrent approach which is also monitoring the window at the input by applying input vectors considering circuit under test as most important part of the processor which is arithmetic logic unit. Findings: The particular locations of the input vectors are stored in the latches which worked as the memory elements and this proposed scheme becomes more efficient by using cellular automata as test pattern generation and response analyzer using rule 90. Application/Improvement: The proposed scheme is comparable with the same architecture, considering TPG as LFSR (Linear Feedback Shift Register) and counter.
9 citations