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Proceedings ArticleDOI

Novel low temperature techniques for growth of ultrathin oxides for strained Si MOS devices

TL;DR: In this article, the authors used thermal oxidation, chemical oxidation and both followed by anodic oxidation to obtain significant improvement in interface states and reliability characteristics of MOS capacitors with ultrathin oxide grown by different techniques.
Abstract: MOS capacitors with ultrathin (cong1.2 nm) oxide grown by different techniques have been fabricated on Strained Si/Relaxed SiGe/n-Si substrates with linearly graded SiGe. These techniques involve thermal oxidation, chemical oxidation and both followed by anodic oxidation. Significant improvement in interface states has been obtained when oxidation was followed by anodic oxidation. The leakage currents and reliability characteristics have also shown great improvement. Band gap offsets extracted using a simple and novel technique are found to match well with expected values.
References
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Journal ArticleDOI
TL;DR: In this paper, the leakage current of the SiO2 layer formed with 61 wt'% HNO3 at its boiling temperature of 113'°C has a 1.3 nm thickness with a considerably high density leakage current.
Abstract: Ultrathin silicon dioxide (SiO2) layers with excellent electrical characteristics can be formed using the nitric acid oxidation of Si (NAOS) method, i.e., by immersion of Si in nitric acid (HNO3) solutions. The SiO2 layer formed with 61 wt % HNO3 at its boiling temperature of 113 °C has a 1.3 nm thickness with a considerably high density leakage current. When the SiO2 layer is formed in 68 wt % HNO3 (i.e., azeotropic mixture with water), on the other hand, the leakage current density (e.g., 1.5 A/cm2 at the forward gate bias, VG, of 1 V) becomes as low as that of thermally grown SiO2 layers, in spite of the nearly identical SiO2 thickness of 1.4 nm. Due to the relatively low leakage current density of the NAOS oxide layer, capacitance–voltage (C–V) curves can be measured in spite of the ultrathin oxide thickness. However, a hump is present in the C–V curve, indicating the presence of high-density interface states. Fourier transformed infrared absorption measurements show that the atomic density of the SiO...

210 citations

MonographDOI
01 Jan 2001
TL;DR: This chapter discusses the properties of Alloy Layers, Si/SiGe Optoelectronics, BICFET, RTD and Other Devices, and MODFETs.
Abstract: * Chapter 1: Introduction * Chapter 2: Strained Layer Epitaxy * Chapter 3: Electronic Properties of Alloy Layers * Chapter 4: Gate Dielectrics on Strained Layers * Chapter 5: SiGe Heterojunction Bipolar Transistors * Chapter 6: Heterostructure Field Effect Transistors * Chapter 7: BICFET, RTD and Other Devices * Chapter 8: MODFETs * Chapter 9: Contact Metallization on Strained Layers * Chapter 10: Si/SiGe Optoelectronics

78 citations


"Novel low temperature techniques fo..." refers methods or result in this paper

  • ...The value of ΔEc is calculated to be approximately 0.121 eV. These values of ΔEv and ΔEc obtained from our calculations match the values reported in literature for similar structure with strained Si on relaxed SiGe [ 2 ]....

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  • ...This allows both electron and hole confinements, useful for both NMOS and PMOS in strained Si/SiGe CMOS technology [ 2 ]....

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  • ...For this set of devices, the value of v Δ is calculated to be approxima tely 0.126 eV. The conduction band offset is now calculated using the following relation [ 2 ]...

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Journal ArticleDOI
TL;DR: In this paper, the advantages of using SiGe in CMOS technology are examined, and conventional MOSFETs are compared with SiGe heterojunction MOSFLETs with channel lengths between 0.5 and 0.1 /spl mu/m.
Abstract: The advantages to be gained by using SiGe in CMOS technology are examined, Conventional MOSFETs are compared with SiGe heterojunction MOSFETs suitable for CMOS technology and having channel lengths between 0.5 and 0.1 /spl mu/m. Two-dimensional computer simulation demonstrates that the improved mobility in the SiGe devices, due to higher bulk mobility and the elimination of Si/SiO/sub 2/ interface scattering by the inclusion of a capping layer, results in significant velocity overshoot close to the source-end of the channel. The cut-off frequency, f/sub t/, is found to increase by around 50% for n-channel devices while more than doubling for p-channel devices for typical estimates of mobility. The results offer the prospect of a more balanced CMOS and improved circuit speed especially when using dynamic logic.

77 citations

Journal ArticleDOI
TL;DR: In this paper, a comprehensive on-line electrical characterization technique addressing the emerging Si/SiGe MOS technology is presented, which demonstrates that the experimental high frequency and low frequency C-V characteristics of Si and SiGe heterostructure MOS capacitors can provide accurate material-, process-, and device-related information such as: the valence band offset, Si cap layer thickness, substrate doping, and MOSFET threshold voltages.
Abstract: This paper presents a comprehensive on-line electrical characterization technique addressing the emerging Si/SiGe MOS technology. It demonstrates that the experimental high frequency and low frequency C-V characteristics of Si/SiGe heterostructure MOS capacitors can provide accurate material-, process-, and device-related information such as: the valence band offset, Si cap layer thickness, substrate doping, and MOSFET threshold voltages.

48 citations

Journal ArticleDOI
TL;DR: In this article, an analytical model for the threshold voltages in a Si/SiGe/Si MOS structure is presented, which offers very good accuracy as compared to results of one-and two-dimensional numerical simulations.
Abstract: An analytical model for the threshold voltages in a Si/SiGe/Si MOS structure is presented. It offers very good accuracy as compared to results of one- and two-dimensional numerical simulations. It is shown that short-channel effects lower the threshold voltage of the SiGe channel and increase the threshold voltage for parasitic conduction in the Si-cap layer. The model can serve as a useful tool for p-channel Si/SiGe/Si MOSFET design.

46 citations