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Proceedings ArticleDOI

Novel thermally enhanced power package

TL;DR: In this article, the authors present a power package design that enables heat conduction to the top surface of the microelectronic package through the use of a high thermal conductivity path which reduces by more than a factor of ten the junction-to-top thermal resistance compared to standard solutions.
Abstract: Heat generated in microelectronic devices as a result of dissipated power is a major issue in power electronics applications resulting in elevated application PC board temperatures. In order to minimize the down ward heat transfer to the application board an efficient method enabling the upward flow of heat from the silicon die to the top of the microelectronic package and subsequently transferred to the environment via forced convection needs to be employed [1]. The problem is that most of the current packaging technologies have a very poor junction-to-top thermal resistance so it is very difficult to have a substantial portion of the heat flowing to the top of the device [2]. In this paper we present a novel power package design that enables heat conduction to the top surface of the microelectronic package through the use of a high thermal conductivity path which reduces by more than a factor of ten the junction-to-top thermal resistance compared to standard solutions. The thermal resistance junction-to-top is found to be as low as 1 C/W, which is comparable with thermal resistance junction to board. This allows for a significant portion of the dissipated energy in the die to be conducted to the topside of the package where natural or forced convection can transfer the heat to the air. We discuss the design, manufacturability, performance and reliability of the package as well as thermal measurements which demonstrates the ability of the package to dissipate the heat. We also compare this solution with existing solution sin the marketplace.

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Citations
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Proceedings ArticleDOI
03 Mar 2015
TL;DR: In this paper, the main trends and opportunities to integrate in the power electronics systems dedicated to the more electrical aircraft (MEA) are reviewed and assessed thanks to the literature and the expertise of the Avionics and Simulation Products department of Airbus.
Abstract: This paper reviews the main trends and opportunities to integrate in the power electronics systems dedicated to the More Electrical Aircraft (MEA). As a matter of fact, the emergence of this promising concept implies a revision of the usual aircraft architectures. As a consequence, it leads to the creation of new converters and strategies of energy management. In addition, with the challenging objectives announced by aircraft manufacturers, current technologies are not performant enough to ensure the expected requirements. They have to be highly improved or replaced by innovative ideas thanks to new explorations or technological ruptures in terms of topology, material and strategy. Thus, the emerging innovations and future developments in aeronautic are presented in this paper and assessed thanks to the literature and the expertise of the Avionics and Simulation Products department of Airbus.

13 citations

Proceedings ArticleDOI
06 Mar 2011
TL;DR: NexFET Power Block as mentioned in this paper combines these two technologies to achieve higher levels of performance, and in half the space versus discrete MOSFETs, and highlights their performance advantage.
Abstract: Efficiency and power loss in the microelectronic devices is a major issue in power electronics applications. The engineers are challenged every year to increase power density and at the same time reduce the amount of power dissipated in the applications to keep the maximum temperatures under specifications. This situation drives a constant demand for better efficiencies in smaller packages. Traditional approaches to improve efficiency in DC/DC synchronous buck converters include reducing conduction losses in the MOSFETs through lower RDS(ON) devices and lowering switching losses through low-frequency operation. However the incremental improvements in RDS(ON) are at a point of diminishing returns and low RDS(ON) devices have large parasitic capacitances that do not facilitate the high-frequency operation required to improve power density. The drive for higher efficiency and increased power in smaller packages is being addressed by advancements in both silicon and packaging technologies. The NexFET Power Block combines these two technologies to achieve higher levels of performance, and in half the space versus discrete MOSFETs. This article explains these new technologies and highlights their performance advantage.

10 citations

Patent
27 Nov 2012
TL;DR: In this paper, a die paddle and an encapsulant are disposed around the die paddle, and a dummy lead is disposed in the corner region of the semiconductor package, where the distance between the dummy lead and the tie bar is less than a shortest distance between a tie bar and other leads or other tie bars.
Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a die paddle, and an encapsulant disposed around the die paddle. The semiconductor package has a first sidewall and a second sidewall. The second sidewall is perpendicular to the first sidewall. The first sidewall and the second sidewall define a corner region. A tie bar is disposed within the encapsulant. The tie bar couples the die paddle and extends away from the die paddle. A dummy lead is disposed in the corner region. The dummy lead is not electrically coupled to another electrically conductive component within the semiconductor package. The distance between the dummy lead and the tie bar is less than a shortest distance between the tie bar and other leads or other tie bars in the semiconductor package.

6 citations

Patent
Makoto Shibuya1
25 Feb 2016
TL;DR: A multichip package includes a first semiconductor device mounted on a first leadframe, in which a primary heat producing surface of the first device is oriented towards and in contact with a heat dispersing region of the second leadframe.
Abstract: A multichip package includes a first semiconductor device mounted on a first leadframe, in which a primary heat producing surface of the first semiconductor device is oriented towards and in contact with a heat dispersing region of the first leadframe A second semiconductor device is mounted on a second leadframe, in which a primary heat producing surface of the second semiconductor device is oriented towards and in contact with a heat dispersing region of the second leadframe A surface of the heat dispersing region of the first leadframe is exposed on a first side of the multichip package, and a surface of the heat dispersing region of the second leadframe is exposed on a second side of the multichip package that is opposite from the first side

4 citations

Dissertation
23 Aug 2010
TL;DR: In this article, a series-connected power MOSFETs module is proposed for high system performance and reliability, especially in terms of high efficiency and high power density, where low parasitic impedance and thermal management is desired for the lower power loss and device stress.
Abstract: Power module design is needed for high system performance and reliability, especially in terms of high efficiency and high power density. Low parasitic impedance and thermal management is desired for the lower power loss and device stress. For power module with high efficiency and improved breakdown voltage, this thesis proposes a novel series-connected power MOSFETs module. Three IRF7832 MOSFETs (30 V breakdown voltage) in series are simulated in a chopper circuit. The drain-source voltage sharing in switching off-mode shows that the devices can share voltage within their breakdown ranges. The switching characteristics are studied, and the switching energy losses without parasitic inductance and with 5 nH parasitic inductances are 203.38 μJ and 316.49 μJ, respectively. The critical parasitic inductance is the one connecting the source of the upper MOSFET and the drain of the middle MOSFET. The switching energy loss due to critical parasitic inductance is about 44.4% of the total switching energy loss. The layout is designed for the double-substrates directbond module and wire-bonded module using direct-bond-copper (DBC) substrate. Based on layout dimensions and packaging materials, the packaging module’s parasitic parameters are obtained using Ansoft® Q3D extractor. Using parasitic inductance values from simulation, the switching energy losses of direct-bond module and wire-bonded module are 296.18 μJ and 238.99 μJ, respectively. Thermal management is then studied using Ansoft® ePhysics. The MOSFET junction-to-air thermal resistances of the double-substrate direct-bond module and the single-substrate wire-bonded module are 33C/W and 82C/W, respectively. Hence, by comparing the direct-bond module with a wire-bonded power module, direct-bond module shows lower parasitic impedances and better thermal management.

4 citations

References
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Proceedings ArticleDOI
10 Dec 2003
TL;DR: In this article, the characterization of air-cooled vapor chamber heat sink (VCHS) and liquid cooled heat sinks (LCHSs) for electronic packages with a targeted power dissipation of 140W is presented.
Abstract: Performance-driven electronic packaging demands for thermal solutions of high power dissipation such as enhanced air cooling or, alternatively, liquid cooling technologies. This paper reports the characterization of air-cooled vapor chamber heat sink (VCHS) and liquid cooled heat sinks (LCHS) for electronic packages with a targeted power dissipation of 140W. The test vehicle flip chip plastic BGA package (FC-PBGA) involves a thermal test chip with a footprint of 12mm/spl times/12mm mounted on a high density substrate of 40mm/spl times/40mm with 1296 I/Os. The VCHS for characterization consists of a copper vapor chamber attached to the base of an Aluminum heat sink. Five types of thermal interface materials were used in the characterization study. In liquid cooling testing, two Aluminum LCHSs with microchannel width around 0.2mm were designed, fabricated and assembled with the chip. De-ionized water was used as coolant. Thermal measurements were conducted and the system-level thermal analysis shows that, for the VCHS, the overall thermal resistances ranged from 0.72 to 0.61/spl deg/C/W, and maximum power dissipations around 100W are achieved given allowable chip temperature rise of 60/spl deg/C. For the liquid cooling characterization, both thermal resistances and pressure drops were obtained at different flowrates and the system thermal resistances ranged from 0.42 to 0.35/spl deg/C/W at pressure drop less than 0.1 bar, indicating the achievable power dissipation of 140 to 170W. This study reveals that there exist performance limits for the air cooling techniques and liquid cooling technique is a feasible candidate for cooling next-generation high-performance electronic packages.

57 citations


"Novel thermally enhanced power pack..." refers methods in this paper

  • ...In order to minimize the down ward heat transfer to the application board an efficient method enabling the upward flow of heat from the silicon die to the top of the microelectronic package and subsequently transferred to the environment via forced convection needs to be employed [1]....

    [...]

Proceedings ArticleDOI
07 Aug 2002
TL;DR: In this article, a power packaging technology developed by International Rectifier is introduced for reducing package related losses and thus allowing designers to develop power supplies capable of meeting the demands of latest generation processors.
Abstract: This paper introduces a novel power packaging technology developed by International Rectifier. This new packaging technology breaks ground in reducing package related losses and thus allowing designers to develop power supplies capable of meeting the demands of latest generation processors.

34 citations


"Novel thermally enhanced power pack..." refers background in this paper

  • ...Fig 3 shows the results of the simulation for different packaging technologies [3]....

    [...]

Proceedings ArticleDOI
Albert W. Chan1, Jie Wei1
01 Jan 2003
TL;DR: In this article, a feasibility study on alternative cooling methods to air-cooling with heat sinks is provided, focusing on cooling of 64-bit microprocessor at 80nm technology node with projected heat dissipation of 200W.
Abstract: Feasibility study on alternative cooling methods to air-cooling with heat sinks is provided in this paper. The study focuses on cooling of 64-bit microprocessor at 80nm technology node with projected heat dissipation of 200W. An example was presented to illustrate limitation of air-cooling for the 200W microprocessor using an all-Cu heat sink with tall fins. Three alternatives to air-cooling were studied in this work: liquid cooling, two-phase convective flow cooling and refrigeration cooling. Thermodynamic analysis was used to estimate operating conditions and fluid flow rates for each alternative. The information provides a preliminary basis for assessing capabilities and weaknesses among alternatives. Liquid and two-phase cooling simply transfer heat from high to low temperature. In contrast, refrigeration cooling operates as a heat pump, moving heat from low to high temperature. Refrigeration cooling offers capability to cool microprocessor (LSI) chip to temperatures below ambient or freezing. The drawback is more heat must be removed from the system. Liquid cooling operates at close to ambient pressure, while two-phase and refrigeration cooling operate at higher pressures. Challenges to implementation of all three alternatives include availability of low cost, miniature components (pumps or compressors, heat exchanger and condenser), designing for redundancy (or reliability) and ease of installation and field service. In terms of component availability and cost, liquid cooling is preferred choice, followed by two-phase and refrigeration cooling.Copyright © 2003 by ASME

3 citations


"Novel thermally enhanced power pack..." refers background in this paper

  • ...The problem is that most of the current packaging technologies have a very poor junction-to-top thermal resistance so it is very difficult to have a substantial portion of the heat flowing to the top of the device [2]....

    [...]