nTunnel FET (nTFET) Reliability Study Against Positive Bias Temperature Instability (PBTI) for Different Device Architectures
01 Jan 2021-pp 159-170
TL;DR: In this paper, the reliability and stability of nTFETs against the adverse effect of positive bias temperature instability (PBTI) for three different device architectures, viz. elevated drain-(ED-), elevated source-(ES-) and elevated source-drain-(ESD-) TFETs, in terms of threshold voltage (VT) shift, on-current/off-current (ION/IOFF) deviation, off-current deviation and minimum subthreshold swing (SSmin) deviation for different PBTI stress conditions.
Abstract: In this paper, for the first time, the nTFET reliability and stability have been studied against the adverse effect of positive bias temperature instability (PBTI) for three different device architectures, viz. elevated drain-(ED-), elevated source-(ES-) and elevated source–drain-(ESD-) TFETs, in terms of threshold voltage (VT) shift, on-current/off-current (ION/IOFF) deviation, off-current (IOFF) deviation and minimum subthreshold swing (SSmin) deviation for different PBTI stress conditions. The channel lengths for all the devices have been considered as 70 nm. It is found that the ES-TFET is showing maximum stability against the PBTI effect in terms of IOFF and ION with a VT shift of 2.9% and SSmin shift of 27%, while maintaining measurable absolute values of the aforementioned device parameters.
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TL;DR: In this paper, a silicon-based Asymmetric-Elevated-Source-Drain Tunnel Field Effect Transistor (AESD-TFET) for gate lengths (LGs), viz. 70, 45, 32, 22, and 13nm, is investigated for the first time.
Abstract: In this paper, silicon-based Asymmetric-Elevated-Source-Drain Tunnel Field-Effect Transistor (AESD-TFET), for gate lengths (LGs), viz. 70, 45, 32, 22, and 13 nm, is investigated for the first time ...
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TL;DR: In this paper, a 70-nm n-channel tunneling field effect transistor (TFET) with sub-threshold swing (SS) of 52.8 mV/dec at room temperature was demonstrated.
Abstract: We have demonstrated a 70-nm n-channel tunneling field-effect transistor (TFET) which has a subthreshold swing (SS) of 52.8 mV/dec at room temperature. It is the first experimental result that shows a sub-60-mV/dec SS in the silicon-based TFETs. Based on simulation results, the gate oxide and silicon-on-insulator layer thicknesses were scaled down to 2 and 70 nm, respectively. However, the ON/ OFF current ratio of the TFET was still lower than that of the MOSFET. In order to increase the on current further, the following approaches can be considered: reduction of effective gate oxide thickness, increase in the steepness of the gradient of the source to channel doping profile, and utilization of a lower bandgap channel material
1,583 citations
TL;DR: In this paper, a dual material gate (DMG) was applied to a tunnel field effect transistor (TFET) to simultaneously optimize the on-current, the off-current and the threshold voltage.
Abstract: In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.
382 citations
TL;DR: In this paper, the effects of varying the dielectric constant and width of the spacer are studied, and it is observed that the use of a low-dielectric as a spacer causes an improvement in its on-state current.
Abstract: A tunnel field-effect transistor (TFET) for which the device operation is based upon a band-to-band tunneling mechanism is very attractive for low-power ultralarge-scale integration circuits. A detailed investigation, with the help of extensive device simulations, of the effects of a spacer dielectric on the device performance of a TFET is reported in this paper. The effects of varying the dielectric constant and width of the spacer are studied. It is observed that the use of a low- dielectric as a spacer causes an improvement in its on-state current. The device performance is degraded with an increase in the spacer width until a certain value (~30 nm); after which, the dependence becomes very weak. The effects of varying the source doping concentration as well as the gate overlap/underlap are also investigated. Higher source doping or a gate-source overlap reduces the spacer dependence of the device characteristics. A gate underlap structure, however, shows an improved performance for a high- spacer. For a given spacer, although a gate overlap or a relatively large gate underlap degrades the device performance, a small gate underlap shows an improvement in it.
139 citations
TL;DR: A new n-type classical-MOSFET-alike tunnel FET architecture is proposed, which offers sub-60mV/decade subthreshold swing along with a significant improvement in I"O"N and it is observed that the device is nearly free from short channel effect (SCE) and its immunity towards drain induced barrier lowering (DIBL) increases with increasing germanium mole fraction.
104 citations
TL;DR: In this article, the role of the channel on the drainpotential dependence of double-gate TFET characteristics is investigated, and it is found that a good drain current saturation is observed only for devices in which a relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel.
Abstract: Because of its different current injection mechanism, a tunnel field-effect transistor (TFET) can achieve a sub-60-m/decade subthreshold swing at room temperature, which makes it very attractive in replacing a metal-oxide semiconductor field-effect transistor, particularly for low-power applications It is well known that some specific TFET structures show a good drain current ID saturation in the output characteristics, whereas other structures do not A detailed investigation, through extensive device simulations, of the role of the channel on the drain-potential dependence of double-gate TFET characteristics is presented in this paper for the first time It is found that a good saturation of ID is observed only for devices in which a thin silicon body is used A relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel, which does not allow the drain current to saturate, even at higher drain voltages
79 citations