NVSim-VX s : An improved NVSim for variation aware STT-RAM simulation
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TLDR
A new member of NVSim family is introduced - NVSim-VXs, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption, and strongly supports the fast-growing needs of STt-RAM research on reliability analysis and enhancement.Abstract:
Spin-transfer torque random access memory (STT-RAM) recently received significant attentions for its promising characteristics in cache and memory applications. As an early-stage modeling tool, NVSim has been widely adopted for simulations of emerging nonvolatile memory technologies in computer architecture research, including STT-RAM, ReRAM, PCM, etc. In this work, we introduce a new member of NVSim family -- NVSim-VXs, which enables statistical simulation of STT-RAM for write performance, errors, and energy consumption. This enhanced model takes into account the impacts of parametric variabilities of CMOS and MTJ devices and the chip operating temperature. It is also calibrated with Monte-Carlo Simulations based on macro-magnetic and SPICE models, covering five technology nodes between 22nm and 90nm. NVSim-VXs strongly supports the fast-growing needs of STT-RAM research on reliability analysis and enhancement, announcing the next important stage of NVSim development.read more
Citations
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References
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Journal ArticleDOI
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Nonvolatile Memory
TL;DR: NVSim is developed, a circuit-level model for NVM performance, energy, and area estimation, which supports various NVM technologies, including STT-RAM, PCRAM, ReRAM, and legacy NAND Flash and is expected to help boost architecture-level NVM-related studies.
Proceedings ArticleDOI
Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events
TL;DR: A novel methodology based on an efficient form of importance sampling, mixture importance sampling is proposed for statistical SRAM design and analysis, which is comprehensive, computationally efficient and in excellent agreement with standard Monte Carlo techniques.
Proceedings ArticleDOI
STT-RAM cell design optimization for persistent and non-persistent error rate reduction: a statistical design view
TL;DR: This work systematically analyze the impacts of CMOS and MTJ process variations, MTJ switching uncertainties induced by thermal fluctuations and working temperature on the performance and reliability of STT-RAM cells.
Journal ArticleDOI
Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies
TL;DR: By using the model, the scalability of STT-RAM technology down to a 22-nm Bulk-CMOS technology node is analyzed and the tradeoffs among the MTJ switching current, the thermal stability of theMTJ and the MOS transistor driving strength are discussed.
Proceedings ArticleDOI
Improving STT MRAM storage density through smaller-than-worst-case transistor sizing
TL;DR: Results show that, under a normalized write current threshold deviation of 20%, the overall memory die size can be reduced by more than 20% compared with the conventional worst-case transistor sizing design practice.