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Journal ArticleDOI

OFF-State Leakage and Performance Variations Associated With Germanium Preamorphization Implant in Silicon–Germanium Channel pFET

TL;DR: In this paper, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe p-type field effect transistor (pFET) process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random drain leakage and performance variations.
Abstract: Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon–germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage ( $\text{V}_{T}$ ) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage ( ${I}_{ \mathrm{\scriptscriptstyle OFF}} $ ) variability and in the halo region at the drain sidewall for $\text{V}_{T}$ variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ random variability for scaled voltages.
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Journal ArticleDOI
TL;DR: In this paper, the matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured, and the matching results have been verified by measurements and calculations on several basic circuits.
Abstract: The matching properties of the threshold voltage, substrate factor, and current factor of MOS transistors have been analyzed and measured. Improvements to the existing theory are given, as well as extensions for long-distance matching and rotation of devices. Matching parameters of several processes are compared. The matching results have been verified by measurements and calculations on several basic circuits. >

3,121 citations


"OFF-State Leakage and Performance V..." refers background in this paper

  • ...In order to investigate the effect of Ge PAI on random variation of leakage and performance, a Pelgrom plot [22] of VT mismatch in linear region for both the splits is made....

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Journal ArticleDOI
TL;DR: In this paper, the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs was investigated.
Abstract: In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates.

612 citations


"OFF-State Leakage and Performance V..." refers background in this paper

  • ...11 with ρ = −0.06, indicating that RDF and MGG are the dominant sources of variability as compared to LER....

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  • ...+ σ 2(tSiGe) + σ 2(Si) (1) where σ is the standard deviation of the electrical parameter and σ (Si) could be due to σ (RDF), σ (LER), and/or σ (MGG) depending on the device design and architecture....

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  • ...Now, in order to find the dominant variability source between RDF and LER, we extract scatterplots of measured DIBL and linear threshold voltage (VTlin) for many identical devices for both the splits....

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  • ...Sources of random variation could be due to random fluctuation (RDF) of number and position of dopant atoms [5], line-edge roughness (LER) [6], [7], metal gate granularity (MGG) [8], [9], and other contributors to work function (WF) variation [10]....

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  • ...LER generally exhibits strong correlation between DIBL and VTlin [25]....

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Journal ArticleDOI
TL;DR: In this article, it has been shown that V/sub th/ fluctuation is mainly caused by the statistical fluctuation of the channel dopant number which explains about 60% of the experimental results.
Abstract: Threshold voltage fluctuation has been experimentally studied, using a newly developed test structure utilizing an 8 k-NMOSFET array. It has been experimentally shown that both V/sub th/ and the channel dopant number n/sub a/ distributions are given as the Gaussian function, and verified that the standard deviation of n/sub a/, can be expressed as the square root of the average of n/sub a/, which is consistent with statistics. In this study, it has been shown that V/sub th/ fluctuation (/spl delta/V/sub th/) is mainly caused by the statistical fluctuation of the channel dopant number which explains about 60% of the experimental results. Moreover, we discuss briefly a new scaling scenario, based on the experimental results of the channel length, the gate oxide thickness, and the channel dopant dependence of /spl delta/V/sub th/. Finally, we discuss V/sub th/ fluctuation caused by the independent statistical-variations of two different dopant atoms in the counter ion implantation process. >

577 citations


"OFF-State Leakage and Performance V..." refers background in this paper

  • ...Sources of random variation could be due to random fluctuation (RDF) of number and position of dopant atoms [5], line-edge roughness (LER) [6], [7], metal gate granularity (MGG) [8], [9], and other contributors to work function (WF) variation [10]....

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Journal ArticleDOI
TL;DR: The importance of process variation in modern transistor technology is discussed, front-end variation sources are reviewed, device and circuit variation measurement techniques are presented, and recent intrinsic transistor variation performance from the literature is compared.
Abstract: Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

350 citations


"OFF-State Leakage and Performance V..." refers background in this paper

  • ...CONTINUED CMOS scaling for high performance, low power, and cost-effective utilization of scaling has resulted in increased statistical variability of the transistor’s electrical parameters [1]–[4]....

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01 Jan 2006

218 citations


"OFF-State Leakage and Performance V..." refers background in this paper

  • ...CONTINUED CMOS scaling for high performance, low power, and cost-effective utilization of scaling has resulted in increased statistical variability of the transistor’s electrical parameters [1]–[4]....

    [...]