On Computer Multiplication and Division Using Binary Logarithms
About: This article is published in IEEE Transactions on Electronic Computers.The article was published on 1963-06-01. It has received 154 citations till now. The article focuses on the topics: Multiplication & Division (mathematics).
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TL;DR: A review and classification are presented for the current designs of approximate arithmetic circuits including adders, multipliers, and dividers including improvements in delay, power, and area for the detection of differences in images by using approximate dividers.
Abstract: Often as the most important arithmetic modules in a processor, adders, multipliers, and dividers determine the performance and energy efficiency of many computing tasks. The demand of higher speed and power efficiency, as well as the feature of error resilience in many applications (e.g., multimedia, recognition, and data analytics), have driven the development of approximate arithmetic design. In this article, a review and classification are presented for the current designs of approximate arithmetic circuits including adders, multipliers, and dividers. A comprehensive and comparative evaluation of their error and circuit characteristics is performed for understanding the features of various designs. By using approximate multipliers and adders, the circuit for an image processing application consumes as little as 47% of the power and 36% of the power-delay product of an accurate design while achieving similar image processing quality. Improvements in delay, power, and area are obtained for the detection of differences in images by using approximate dividers.
197 citations
Cites methods from "On Computer Multiplication and Divi..."
...Some recent designs use shifting and addition to obtain the final product by rounding the inputs to a form of 2m (m is a positive integer) [Hashemi et al. 2015; Zendeganie et al. 2017; Mitchell 1962]....
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01 Jan 2014
TL;DR: In this article, the authors proposed a method to improve the quality of the information provided by the user by using the information from the user's profile and the user profile of the service provider.
Abstract: Натрийуретические пептиды (НУП) являются важными биомаркерами в диагностике и определении прогноза у пациентов с сердечной недостаточностью (СН). Оценка динамики концентрации НУП (BNP, Nt -proBNP) может быть использована в качестве критерия успешности проводимой терапии. так, при достижении целевых уровней НУП можно прогнозировать благоприятный исход заболевания. В настоящее время лечение СН с учетом уровней НУП является частью рекомендаций по лечению СН (класс IIа) и улучшению ее исхода (класс IIб) в США, однако такой подход не используется в российских клиниках. Цель. Представить современный взгляд на возможность использования НУП для оценки эффективности проводимой терапии пациентов с СН. Ключевые слова: натрийуретические пептиды, сердечная недостаточность, оценка эффективности терапии.
167 citations
Additional excerpts
...[225; 290], разложение в ряд Тейлора [125; 209], табличная аппроксимация [119; 121; 259], кусочно-линейная аппроксимация [107]....
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...Наиболее простым способом аппроксимации двоичного числа, представленного в формате с фиксированной точкой, является метод Митчелла [225]....
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12 Aug 2020
TL;DR: A comprehensive survey and a comparative evaluation of recently developed approximate arithmetic circuits under different design constraints, synthesized and characterized under optimizations for performance and area.
Abstract: Approximate computing has emerged as a new paradigm for high-performance and energy-efficient design of circuits and systems. For the many approximate arithmetic circuits proposed, it has become critical to understand a design or approximation technique for a specific application to improve performance and energy efficiency with a minimal loss in accuracy. This article aims to provide a comprehensive survey and a comparative evaluation of recently developed approximate arithmetic circuits under different design constraints. Specifically, approximate adders, multipliers, and dividers are synthesized and characterized under optimizations for performance and area. The error and circuit characteristics are then generalized for different classes of designs. The applications of these circuits in image processing and deep neural networks indicate that the circuits with lower error rates or error biases perform better in simple computations, such as the sum of products, whereas more complex accumulative computations that involve multiple matrix multiplications and convolutions are vulnerable to single-sided errors that lead to a large error bias in the computed result. Such complex computations are more sensitive to errors in addition than those in multiplication, so a larger approximation can be tolerated in multipliers than in adders. The use of approximate arithmetic circuits can improve the quality of image processing and deep learning in addition to the benefits in performance and power consumption for these applications.
143 citations
Cites background or methods from "On Computer Multiplication and Divi..."
...Mitchell’s binary logarithm-based algorithm enables the utilization of adders and subtractors to implement multipliers and dividers, respectively [11]....
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...4) Using Logarithmic Approximation: Mitchell’s algorithm leverages the logarithmic and anti-logarithmic approximations of a binary number....
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...It serves as the basis of logarithmic multipliers (LMs) [11]....
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...An approximate arithmetic circuit can be obtained by using the voltage overscaling (VOS) technique [58]–[60], redesigning a logic circuit into an approximate one [51], and using a simplification algorithm [11]....
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...In this design, the p MSBs in a 2n/n divider is accurately implemented as a restoring array divider, while the (2n − p) LSBs are approximately processed using Mitchell’s algorithm as per (12)....
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TL;DR: The designs of both non-iterative and iterative approximate logarithmic multipliers (ALMs) are studied to further reduce power consumption and improve performance and it is found that the proposed approximate LMs with an appropriate number of inexact bits achieve higher accuracy and lower power consumption than conventional LMs using exact units.
Abstract: In this paper, the designs of both non-iterative and iterative approximate logarithmic multipliers (ALMs) are studied to further reduce power consumption and improve performance. Non-iterative ALMs, that use three inexact mantissa adders, are presented. The proposed iterative ALMs (IALMs) use a set-one adder in both mantissa adders during an iteration; they also use lower-part-or adders and approximate mirror adders for the final addition. Error analysis and simulation results are also provided; it is found that the proposed approximate LMs with an appropriate number of inexact bits achieve higher accuracy and lower power consumption than conventional LMs using exact units. Compared with conventional LMs with exact units, the normalized mean error distance of 16-bit approximate LMs is decreased by up to 18% and the power-delay product has a reduction of up to 37%. The proposed approximate LMs are also compared with previous approximate multipliers; it is found that the proposed approximate LMs are best suitable for applications allowing larger errors, but requiring lower energy consumption. Approximate Booth multipliers fit applications with less stringent power requirements, but also requiring smaller errors. Case studies for error-tolerant computing applications are provided.
109 citations
Cites background or methods from "On Computer Multiplication and Divi..."
...Note that Mitchell logarithmic multiplier always underestimates the correct value [15]....
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...The exact product can be rewritten as follows [15]:...
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...Mitchell’s algorithm [15] is referred to as a non-iterative...
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...Approximate design techniques can be applied to different parts of a conventional multiplier, such as operands [15]–[20], partial product (PP) generation [21]–[24], PP tree [25]–[30] and compressors [31]–[34]....
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...Mitchell’s algorithm [15] is referred to as a non-iterative logarithmic multiplier in this work....
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TL;DR: The proposed approximate multiplier has an almost Gaussian error distribution with a near-zero mean value and is exploited in the structure of a JPEG encoder, sharpening, and classification applications, indicating that the quality degradation of the output is negligible.
Abstract: A scalable approximate multiplier, called truncation- and rounding-based scalable approximate multiplier (TOSAM) is presented, which reduces the number of partial products by truncating each of the input operands based on their leading one-bit position. In the proposed design, multiplication is performed by shift, add, and small fixed-width multiplication operations resulting in large improvements in the energy consumption and area occupation compared to those of the exact multiplier. To improve the total accuracy, input operands of the multiplication part are rounded to the nearest odd number. Because input operands are truncated based on their leading one-bit positions, the accuracy becomes weakly dependent on the width of the input operands and the multiplier becomes scalable. Higher improvements in design parameters (e.g., area and energy consumption) can be achieved as the input operand widths increase. To evaluate the efficiency of the proposed approximate multiplier, its design parameters are compared with those of an exact multiplier and some other recently proposed approximate multipliers. Results reveal that the proposed approximate multiplier with a mean absolute relative error in the range of 11%–0.3% improves delay, area, and energy consumption up to 41%, 90%, and 98%, respectively, compared to those of the exact multiplier. It also outperforms other approximate multipliers in terms of speed, area, and energy consumption. The proposed approximate multiplier has an almost Gaussian error distribution with a near-zero mean value. We exploit it in the structure of a JPEG encoder, sharpening, and classification applications. The results indicate that the quality degradation of the output is negligible. In addition, we suggest an accuracy configurable TOSAM where the energy consumption of the multiplication operation can be adjusted based on the minimum required accuracy.
99 citations
Cites methods from "On Computer Multiplication and Divi..."
...Mitchell [22] proposed a simple approximate method to calculate the logarithm and antilogarithm of a number and used it to generate the multiplication results (Mitchell multiplier)....
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References
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TL;DR: A method of computer multiplication and division is proposed which uses binary logarithms and an error analysis is given and a means of reducing the error for the multiply operation is shown.
Abstract: A method of computer multiplication and division is proposed which uses binary logarithms. The logarithm of a binary number may be determined approximately from the number itself by simple shifting and counting. A simple add or subtract and shift operation is all that is required to multiply or divide. Since the logarithms used are approximate there can be errors in the result. An error analysis is given and a means of reducing the error for the multiply operation is shown.
488 citations