Journal ArticleDOI
On Division by Functional Iteration
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TLDR
In order to avoid the time delays associated with linearly convergent division based on subtraction, other iterative schemes can be used based on series expansion of the reciprocal, multiplicative sequence, or additive sequence convergent to the quotient.Abstract:
In order to avoid the time delays associated with linearly convergent division based on subtraction, other iterative schemes can be used. These are based on 1) series expansion of the reciprocal, 2) multiplicative sequence, or 3) additive sequence convergent to the quotient. These latter techniques are based on finding the root of an arbitrary function at either the quotient or reciprocal value. A Newton-Raphson iteration or root finding iteration can be used.read more
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Journal ArticleDOI
Division algorithms and implementations
S.F. Obermann,Michael J. Flynn +1 more
TL;DR: A taxonomy of division algorithms is presented which classifies the algorithms based upon their hardware implementations and impact on system design, finding that, for low-cost implementations where chip area must be minimized, digit recurrence algorithms are suitable.
Journal ArticleDOI
The Sign/Logarithm Number System
TL;DR: A signed logarithmic number system, which is capable of representing negative as well as positive numbers is described, and it is shown that negative numbers can be represented in the sign/logarithm number system.
MonographDOI
FPGA-based Implementation of Signal Processing Systems
TL;DR: FPGA-based Implementation of Signal Processing Systems is an important reference for practising engineers and researchers working on the design and development of DSP systems for radio, telecommunication, information, audio-visual and security applications.
Journal ArticleDOI
A Review, Classification, and Comparative Evaluation of Approximate Arithmetic Circuits
TL;DR: A review and classification are presented for the current designs of approximate arithmetic circuits including adders, multipliers, and dividers including improvements in delay, power, and area for the detection of differences in images by using approximate dividers.
Journal ArticleDOI
Design issues in division and other floating-point operations
TL;DR: The system performance impact of floating-point division latency for varying instruction issue rates is presented and the performance implications of shared multiplication hardware, shared square root, on-the-fly rounding and conversion, and fused functional units are examined.
References
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Book
Iterative Methods for the Solution of Equations
TL;DR: One-point iteration functions with memory have been studied extensively in the literature as discussed by the authors, where it is shown that one-point iterators with memory achieve linear and superlinear convergence with respect to a fixed-point problem.
Journal ArticleDOI
A Suggestion for a Fast Multiplier
TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.
Journal ArticleDOI
Very high-speed computing systems
TL;DR: In this paper, the authors classified very high-speed computers as follows: 1) Single Instruction Stream-Single Data Stream (SISD) 2) SIMD 3) MIMD 4) MISD-MIMD.
Journal ArticleDOI
A Suggestion for a Fast Multiplier
TL;DR: The author develops an adder tree to sum this set when t= 1 the maximum number of regions intersections of n t-flats and shows that a tree will be dependent on both t and n.
Journal ArticleDOI
The IBM system/360 model 91: floating-point execution unit
TL;DR: The principal requirement for the Model 91 floating-point execution unit was that it be designed to support the instructionissuing rate of the processor, so separate, instruction-oriented algorithms for the add, multiply, and divide functions were developed.