![Fig. 2. (a) Simulation of Si Zener diode fitted to experimental data from Fair and Wivell [13]. (b) Transient response characteristics of silicon TFET- and MOSFET-based inverters. The load capacitance CL is set to zero in this simulation. (c) Inverter schematic showing the origin of the overshoot/undershoot in TFET. (d) Si TFET and Si MOSFET inverter VTCs.](/figures/fig-2-a-simulation-of-si-zener-diode-fitted-to-experimental-2ejxktlr.webp)
1102 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 10, OCTOBER 2009
On Enhanced Miller Capacitance Effect
in Interband Tunnel Transistors
Saurabh Mookerjea, Student Member, IEEE, Ramakrishnan Krishnan, Student Member, IEEE,
Suman Datta, Senior Member, IEEE, and Vijaykrishnan Narayanan, Senior Member, IEEE
Abstract—We compare the transient response of double-gate
thin-body-silicon interband tunnel field-effect transistor (TFET)
with its metal–oxide–semiconductor field-effect transistor coun-
terpart. Due to the presence of source side tunneling barrier,
the silicon TFETs exhibit enhanced Miller capacitance, resulting
in large voltage overshoot/undershoot in its large-signal switch-
ing characteristics. This adversely impacts the performance of
Si TFETs for digital logic applications. It is shown that TFETs
based on lower bandgap and lower density of states materials
like indium arsenide show significant improvement in switching
behavior due to its lower capacitance and higher ON current at
reduced voltages.
Index Terms—Density of states (DOS), InAs, metal–oxide–
semiconductor field-effect transistors (FETs) (MOSFETs), Miller
capacitance, silicon, tunnel FETs (TFETs).
I. INTRODUCTION
I
NTERBAND tunnel field-effect transistors (TFETs) with a
gate-modulated Zener tunnel junction at the source have
recently attracted a great deal of interest [1]–[7]. The major
advantage of TFETs in comparison with the metal–oxide–
semiconductor field-effect transistors (MOSFETs) is that the
reverse biased tunnel junction in the former eliminates the
high-energy tail present in the Fermi–Dirac distribution of
the valence band electrons in the p+ source region and allows
sub-kT/q subthreshold slope device operation near the
OFF state. This allows TFETs to achieve, in principle, much
higher I
ON
−I
OFF
ratio over a specified gate voltage swing
compared to MOSFETs, making the former attractive for
low-V
DD
operation.
To date, the published work on TFETs has focused on device
level dc transfer characteristics and not on circuit level ac
switching performance. In this letter, for the first time, we
compare the large-signal switching behavior of silicon-based
TFETs with MOSFETs in an inverter configuration using a
2-D numerical device simulator [8]. We reveal that the TFET
performance is limited by the enhanced gate-to-drain Miller
capacitance (C
gd
) effect which leads to significant voltage
Manuscript received June 5, 2009. First published September 4, 2009;
current version published September 29, 2009. This work was supported in
part by the Nanoelectronics Research Initiative through the Midwest Institute
for Nanoelectronics Discovery. The review of this letter was arranged by Editor
E. Sangiorgi.
The authors are with the Department of Electrical Engineering, The
Pennsylvania State University, University Park, PA 16802 USA (e-mail:
sam567@psu.edu; ruk142@psu.edu; sdatta@engr.psu.edu; vijay@cse.
psu.edu).
Color versions of one or more of the figures in this letter are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2009.2028907
overshoot and undershoot in its transient response and explain
its physical origin from basic TFET device physics. It is shown
that the high voltage overshoot/undershoot in TFET inverter
characteristics can be mitigated through a reduction in C
gd
-
dominated Miller effect through capacitive loading of the TFET
inverter at the expense of increased inverter delay. A promising
way to circumvent this problem is to go to lower bandgap
materials and lower density of states (DOS) material such as
InAs, which provide reduced source side tunnel barrier and
reduced Miller capacitance, respectively.
II. C
APACITANCE VOLTAGE CHARACTERISTICS
Fig. 1(a) shows the device structure used for this letter and
the dc I
DS
–V
GS
characteristics for Si MOSFET and TFET.
Both TFET and MOSFET have a double-gate structure with
a gate length (L
G
) of 30 nm, 2.5-nm-thick HfO
2
gate dielec-
tric, and an intrinsically doped body which is 7 nm thick.
Gaussian doping profiles with a peak density of 10
20
cm
−3
for
Si TFET/MOSFET and 10
19
cm
−3
for InAs TFET and doping
gradients of 2 nm/dec with an overlap of 2 nm on each side
are used for the s ource/drain regions. The interband tunneling
current in the TFET depends on the potential profile along
the entire path between two points connected by tunneling.
In contrast to the local tunneling models commonly used [9],
[10], we use a nonlocal tunneling model [11] which reflects
the real space carrier transport through the barrier, taking
into account the potential profile along the entire tunneling
path. The band edge tunneling masses of m
c
= 0.5m
0
and
m
v
= 0.65m
0
(where m
0
is the electron rest mass) for sili-
con and m
c
= m
v
= 0.023m
0
for InAs are used to calculate
the local imaginary wavenumbers within the forbidden gap.
Kane’s two-band model is then used to calculate the tunneling
probability. The results presented here are obtained through
a drift–diffusion simulation, where the Poisson and carrier
continuity equations are solved self-consistently. An interband
tunneling component is added to the carrier continuity equation
as a generation–recombination (G-R) term. The G-R term
contains adjustable scaling factors g
c
and g
v
kept at values
equal to 0.1 and 0.4, respectively, for Si and equal to 1 for
InAs, which set the effective Richardson constant. Fig. 2(a)
shows the excellent fit of our nonlocal tunneling model with
the experimental data from Fair and Wivell [13] for a reverse
biased Si Zener diode.
Fig. 1(b) and (c) shows the capacitance voltage character-
istics of silicon-based MOSFET with TFETs. For capacitance
simulation, a sinusoidal steady-state analysis (S
3
A) technique
0741-3106/$26.00 © 2009 IEEE
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MOOKERJEA et al.: ENHANCED MILLER CAPACITANCE EFFECT 1103
Fig. 1. (a) DC I
DS
–V
GS
characteristics for p-type and n-type Si TFET and MOSFET. Inset shows the device schematic; the details are explained in the text.
(b) Capacitance–voltage characteristics showing the gate (C
gg
), gate-to-source (C
gs
), and gate-to-drain (C
gd
) capacitances as a function o f gate-to-source
voltage V
GS
for (b) Si MOSFET and (c) Si TFET.
Fig. 2. (a) Simulation of Si Zener diode fitted to experimental data from Fair
and Wivell [13]. (b) Transient response characteristics of silicon TFET- and
MOSFET-based inverters. The load capacitance C
L
is set to zero in this simu-
lation. (c) Inverter schematic showing the origin of the overshoot/undershoot in
TFET. (d) Si TFET and Si MOSFET inverter VTCs.
[12] is employed, which applies a sinusoidal voltage perturba-
tion of infinitesimal amplitude to the device terminals in the
frequency domain and monitors the terminal currents to yield
the admittance matrix containing the capacitance and conduc-
tance. The insets in Fig. 1(b) and (c) depict the energy band
diagrams for MOSFET and TFET. In the
OFF state (V
GS
= 0V;
V
DS
= 1V), the conduction in MOSFET is limited by the
source side p-n junction barrier which prevents the thermionic
emission of carriers. In the
ON state (V
GS
= 1; V
DS
= 1),the
source barrier is negligible, enabling over the barrier thermionic
emission. In contrast, TFETs operate by tunneling of carriers
from the valence band in the source to the conduction band in
the channel. In the
OFF state (V
GS
= 0V; V
DS
= 1V), trans-
mission probability is low due to the thick depletion region as-
sociated with the source to channel tunnel junction, resulting in
very low OFF currents. In the
ON state (V
GS
= V
DS
= 1V),the
tunnel barrier shrinks, allowing carriers to tunnel through. Since
the TFET ON current is limited by the interband quantum–
mechanical tunneling compared to thermionic emission over
the barrier, the ON current in silicon TFETs is much lower than
MOSFETs. This results in very low gate-to-source capacitance
(C
gs
) in TFETs in the ON state (V
GS
= V
DS
= 1V) compared
to MOSFETs [Fig. 1(b) and (c)]. Furthermore, there is very
little potential drop between the channel and the drain in TFETs
compared to the large reverse bias that exists between the
channel and the drain in MOSFETs, as observed from the band
diagrams. This results in large gate-to-drain capacitance (C
gd
)
or Miller capacitance in TFETs compared to MOSFETs. It is
worthwhile to note that the gate capacitance C
gg
is entirely re-
flected by the gate-to-drain capacitance C
gd
in TFETs under all
bias conditions in stark contrast to MOSFETs, where both C
gs
and C
gd
contribute. The C
gd
dominates even near the OFF-state
condition in TFETs at V
GS
= V
DS
= 0 V, since the source-to-
channel barrier resistance is large while the channel-to-drain
barrier resistance is low. The latter is set by the combination of
gate electrode work function (band edge n-type work function
gate metal) and 10
15
cm
−3
of near intrinsic channel doping.
This results in low C
gs
and high C
gd
for TFETs at low V
GS
.
On the contrary, in MOSFETs at V
GS
= V
DS
= 0, the potential
barriers for both the source-to-channel and drain-to-channel
p-n junctions are approximately equal to E
g
/2 set by the gate
electrode work function (mid-gap workfunction metal) and
10
15
cm
−3
of p-type channel doping. This results in both C
gs
and C
gd
being equal but small for MOSFETs. This enhanced
Miller capacitance (C
gd
) effect in TFETs over MOSFETs,
coupled with low ON currents, has important implications for
their large-signal transient response.
III. I
MPACT ON TRANSIENT RESPONSE
Fig. 2(b) shows the transient response of silicon TFETs with
MOSFET in an i nverter configuration to an input ramp voltage
(1-V peak voltage and 5-ps rise time). TFETs exhibit very large
output voltage overshoot and undershoot peaks when the input
voltage pulse begins to transition from 0–1 and 1–0 V, respec-
tively. The overshoot peak arises primarily due to the large
C
gd
(Miller capacitance) in TFETs compared to MOSFETs.
The origin of this voltage overshoot is depicted in the circuit
schematic of Fig. 2(c), where the input transient voltage is
directly coupled to the output node by the high C
gd
of the load
TFET operating in the linear region. The output voltage of the
TFET inverter stays at a very high value V
MAX
at the end of
the input 0–1 transition. This continues to keep the pull-down
n-TFET in deep saturation (low C
gd
) while the pull-up p-TFET
remains in the linear region (high C
gd
). Even as the output
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1104 IEEE ELECTRON DEVICE LETTERS, VOL. 30, NO. 10, OCTOBER 2009
Fig. 3. (a) Peak overshoot and fall time delay as functions of load capacitance
C
L
for Si (a) MOSFET and (b) TFET inverters. Fall time delay is measured
as the time interval between 50% of input (V
in
) and 50% of output (V
out
)
voltages of the inverter in Fig. 2.
voltage starts transitioning from its peak overshoot value, the
C
gd
for p-TFET decreases while that for n-TFET increases,
thereby maintaining a high Miller capacitance all throughout
the transient. Fig. 2(d) shows the voltage transfer characteristics
of the correctly sized Si-based TFET and MOSFET inverters. In
TFETs, the extent of this overshoot can be calculated from the
following charge conservation equation [14]:
C
L
V
MAX
+ C
M
(V
MAX
− V
DD
)=(C
M
+ C
L
)V
DD
V
P
= V
MAX
− V
DD
=
C
M
C
M
+ C
L
V
DD
(1)
where C
M
is the Miller capacitance connecting the input and
output of the inverter comprising the gate-to-drain capacitance
of both p-TFET and n-TFET, C
L
is the load capacitance
external to the device, V
MAX
is the maximum voltage to
which t he output voltage rises, V
P
is the peak value of the
overshoot, and V
DD
is the supply voltage. This equation clearly
shows the impact of higher Miller capacitance on the peak
overshoot voltage in TFETs. The effect of this Miller capaci-
tance in TFETs is significantly reduced by loading the TFET
inverter with an appropriate load capacitance C
L
. However,
this leads to degraded fall time delays for TFET. Fig. 3(a)
and (b) shows the tradeoff between peak overshoot voltage
and fall time delay (time interval between 50% input and 50%
output) in silicon MOSFET and TFET inverters as a function
of C
L
. The fall time delay in silicon TFET inverter is worse
by an order of magnitude compared to MOSFET due to the
low ON current in Si TFETs (Si TFET I
ON
∼ 60 µA/µm;
Si MOSFET ∼ 1.13 mA/µm) and higher C
gd
. This warrants
the need for exploration of an alternate solution, which would
fundamentally limit the gate-to-drain capacitance in TFETs and
reduce the Miller capacitance effect.
Low bandgap and low effective mass materials such as
indium arsenide (InAs) are promising for TFET due to higher
tunneling rate t hrough the source side tunnel barrier and higher
ON current (82 µA/µm) at V
DD
= 0.25 V [7]. Furthermore,
the reduced DOS in InAs limits the gate-to-drain capacitance
and mitigates the enhanced Miller capacitance effect [Fig. 4(a)].
This suppresses the voltage overshoot/undershoot in the tran-
sient switching characteristics and improves the inverter fall
time delay significantly by ∼45 times to 1.1 ps [Fig. 4(b)] from
1.4 times increase in ON current, eight times reduction in C
gd
,
and four times reduction in V
DD
.
Fig. 4. (a) Capacitance–voltage characteristics of an InAs TFET showing the
gate (C
gg
), gate-to-source (C
gs
), and gate-to-drain (C
gd
) capacitances as a
function of gate-to-source voltage V
GS
. Note that the supply voltage is V
DD
=
0.25 V. (b) Transient response characteristics of an InAs TFET inverter. InAs
TFET exhibits a significantly smaller voltage overshoot/undershoot due to
smaller Miller capacitance and higher I
ON
compared to Si TFETs. The fall
time delay is improved significantly to 1.1 ps.
IV. CONCLUSION
In summary, we have shown that the transient performance
of TFET inherently suffers from an enhanced Miller capac-
itance, resulting in large output voltage overshoot/undershoot
and increased inverter delay. Following the charge conservation
principle, it has been shown that V
P
can be reduced by capaci-
tive loading of the TFET inverter at the expense of increased
fall time delay. A more promising approach is identified in
an InAs-based TFET due to its higher ON current and lower
Miller capacitance at reduced supply voltages, stemming from
its reduced DOS.
R
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