Proceedings ArticleDOI
On the Applicability of Triangular Carbon Nanotube Bundles as VLSI interconnects
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TLDR
In this paper, triangular cross sectioned carbon nanotube (T-CNT) bundles are proposed as VLSI interconnects and compared with square cross-sectioned CNT bundles.Abstract:
Triangular cross sectioned carbon nanotube bundles are proposed as VLSI interconnects. Due to their inherent geometry effects, triangular CNT (T-CNT) bundles are least capacitively coupled and hence offer least possible coupling capacitance between adjacent interconnects. So, this transpires to lesser crosstalk and induced delay in T-CNT bundle interconnects compared to traditionally proposed CNT bundle interconnect structures. So, in this work, we study the feasibility of using T-CNT bundles as interconnects in ICs. For that, we analyze the AC frequency response of T-CNT bundles and compare them with traditionally used square cross sectioned CNT (S-CNT) bundles. HSPICE based circuit simulations are carried out at various input voltages ranging from subthreshold to superthreshold voltages of 0.3V, 0.6V and 0.9V. Also, we do the analysis for local, semi-global and global interconnect lengths ranging from $500\mu\mathrm{m}$ to $2000\mu\mathrm{m}$ . Results show that T-CNT bundles have higher voltage gain for all lengths compared to S-CNT bundles. More specifically, T-CNT bundles have highest voltage gain at 0.3V for all lengths. This shows that T-CNT bundles are suitable as VLSI interconnects and are more suited at subthreshold voltages.read more
Citations
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Comparison of Various Low Dielectric Constant Materials
Wei-jie Hung,Yi-Lung Cheng +1 more
TL;DR: In this paper, the intrinsic resistance-capacitance delay of back-end-of-line (BEOL) interconnects in integrated circuits is reduced by using low-dielectric-constant (low-k) materials with a dielectric constant (k)
References
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Journal ArticleDOI
Conductance Modeling for Graphene Nanoribbon (GNR) Interconnects
Azad Naeemi,James D. Meindl +1 more
TL;DR: In this article, a model for conductance of GNRs as functions of chirality, width, Fermi level, and the type of electron scatterings at the edges is presented.
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A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.
TL;DR: The fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz is reported, paving the way for future multi-GHz nanoelectronics.
Journal ArticleDOI
Impact of Wire Geometry on Interconnect RC and Circuit Delay
Ivan Ciofi,Antonino Contino,Philippe Roussel,Rogier Baert,Victor-H. Vega-Gonzalez,Kristof Croes,Mustafa Badaroglu,Christopher J. Wilson,Praveen Raghavan,Abdelkarim Mercha,Diederik Verkest,Guido Groeseneken,Dan Mocuta,Aaron Thean +13 more
TL;DR: For a given pitch and dielectric stack height, the RC delay can be significantly reduced by targeting wider and deeper damascene trenches, that is, by trading capacitance for resistance, and that an optimal wire geometry for RC delay minimization exists.
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On-Chip Interconnect Conductor Materials for End-of-Roadmap Technology Nodes
TL;DR: To sustain the continuous downward scaling of integrated circuit feature sizes, alternative interconnect conductor materials to replace copper and tungsten must be explored to meet and overcome these challenges.
Journal ArticleDOI
Active Shielding of MWCNT Bundle Interconnects: An Efficient Approach to Cancellation of Crosstalk-Induced Functional Failures in Ternary Logic
TL;DR: In this article, an efficient active shielding of multi-walled carbon nanotube (MWCNT) bundle interconnects is proposed to cancel the crosstalk-induced functional failures in ternary logic.