On the Charge Sheet Superjunction (CSSJ) MOSFET

Abstract: Gate enhanced power UMOSFET (GE-UMOS) is proposed to decrease the specific on -resistance of the device. The key feature of this structure is that the deep trench polysilicon electrode is contacted to the gate electrode, maintaining the breakdown voltage and forming the high electron current density at side n-drift region, thus resulting in a lower on -resistance compared to the superjunction structure and gradient oxide-bypassed (GOB) structure. Furthermore, the performance of GE-UMOS is proved by comparing with the GOB-UMOS structure.

Abstract: Superjunction has arguably been the most creative and important concept in power device field Superjunction vertical diffused MOSFET (SJ VDMOS) has been commercialized and the research effort to l

Abstract: An optimized gate-enhanced (GE) power UMOSFET with split gate (SGE-UMOS) is proposed. This device shows the reduction in specific on-state resistance (Rsp) at a breakdown voltage of 119 V as compared to the gradient oxide-bypassed (GOB) UMOS and GE-UMOS devices, which is due to the higher N-type concentration in the drift region. In addition, the split-gate floating structure in SGE-UMOS also reduces the gate-source electrode parasitic capacitor. The numerical simulation results indicate that the proposed device features high performance with improved Rsp and Qg as compared to that of the GOB-UMOS and GE-UMOS devices.

Abstract: Aiming for the investigation of insulating properties of aluminum oxide (Al2O3) layers, as well as the combination of this oxide with tin dioxide (SnO2) for application in transparent field effect transistors, Al thin films are deposited by resistive evaporation on top of SnO2 thin films deposited by sol–gel dip-coating process. The oxidation of Al films to Al2O3 are carried out by thermal annealing at 500 °C in room conditions or oxygen atmosphere. X-ray diffraction data indicate that tetragonal Al2O3 is indeed obtained. A simple device and electric circuit is proposed to measure the insulating properties of aluminum oxide and the transport properties of SnO2 as well. Results indicate a fair insulation when four layers or Al2O3 are grown on the tin dioxide film, concomitant with thermal annealing between each layer. The current magnitude through the insulating layer is only 0.2% of the current through the semiconductor film, even though the conductivity of the SnO2 alone is not very high (the average resistivity is 2 Ω cm), because no doping is used. The presented results are a good indication that this combination may be useful for transparent devices.

Abstract: For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (Ron,sp) of 2 mΩ cm2, which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.

Abstract: Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

Abstract: A new theory of semiconductor devices, called "semiconductor superjunction (SJ) theory", is presented. To overcome the trade-off relationship between breakdown voltage and on-resistance of conventional semiconductor devices, SJ devices utilize a number of alternately stacked, p- and n-type, heavily doped, thin semiconductor layers. By controlling the degree of doping and the thickness of these layers, according to the SJ theory, this structure operates as a pn junction with low on-resistance and high breakdown voltage. Analytical formulas for the ideal specific on-resistance and the ideal breakdown voltage of SJ devices are theoretically derived. Analysis based on the formulas and device simulations reveals that the on-resistance of SJ devices can be reduced to less than 10-2 that of conventional devices.

Abstract: High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

Abstract: For the first time a new device concept for high voltage power devices has been realized in silicon. Our 600 V-COOLMOS/sup TM/ reaches an area specific on-resistance of typically 3.5 /spl Omega//spl middot/mm/sup 2/. Our technology thus offers a shrink factor of 5 versus the actual state of the art in power MOSFETs. The device concept is based on charge compensation in the drift region of the transistor. We increase the doping of the vertical drift region roughly by one order of magnitude and counterbalance this additional charge by the implementation of fine structured columns of the opposite doping type. The blocking voltage of the transistor remains thus unaltered. The charge compensating columns do not contribute to the current conduction during the turn-on state. Nevertheless the drastically increased doping of the drift region allows the above mentioned reduction of the on-resistance.

Abstract: Surface recombination velocities as low as 10 cm/s have been obtained by treated atomic layer deposition (ALD) of Al 2 O 3 layers on p-type CZ silicon wafers. Low surface recombination is achieved by means of field induced surface passivation due to a high density of negative charges stored at the interface. In comparison to a diffused back surface field, an external field source allows for higher band bending, that is, a better performance. While this process yields state of the art results, it is not suited for large-scale production. Preliminary results on an industrially viable, alternative process based on a pseudo-binary system containing Al 2 O 3 are presented, too. With this process, surface recombination velocities of 500–1000 cm/s have been attained on mc-Si wafers.