On the Optimal Design of Triple Modular Redundancy Logic for SRAM-based FPGAs
07 Mar 2005-Vol. 2, pp 1290-1295
TL;DR: The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 4.03% to 0.98% the number of upsets in the routing able to cause an error in theTMR circuit.
Abstract: Triple modular redundancy (TMR) is a suitable fault tolerant technique for SRAM-based FPGA However, one of the main challenges in achieving 100% robustness in designs protected by TMR running on programmable platforms is to prevent upsets in the routing from provoking undesirable connections between signals from distinct redundant logic parts, which can generate an error in the output This paper investigates the optimal design of the TMR logic (eg, by cleverly inserting voters) to ensure robustness Four different versions of a TMR digital filter were analyzed by fault injection Faults were randomly inserted straight into the bitstream of the FPGA The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 403% to 098% the number of upsets in the routing able to cause an error in the TMR circuit
Citations
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TL;DR: A reliability-oriented place and route algorithm is presented that is able to effectively mitigate the effects of the considered faults and is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique.
Abstract: The very high integration levels reached by VLSI technologies for SRAM-based field programmable gate arrays (FPGAs) lead to high occurrence-rate of transient faults induced by single event upsets (SEUs) in FPGAs' configuration memory. Since the configuration memory defines which circuit an SRAM-based FPGA implements, any modification induced by SEUs may dramatically change the implemented circuit. When such devices are used in safety-critical applications, fault-tolerant techniques are needed to mitigate the effects of SEUs in FPGAs' configuration memory. In this paper, we analyze the effects induced by the SEUs in the configuration memory of SRAM-based FPGAs. The reported analysis outlines that SEUs in the FPGA's configuration memory are particularly critical since they are able to escape well-known fault masking techniques such as triple modular redundancy (TMR). We then present a reliability-oriented place and route algorithm that, coupled with TMR, is able to effectively mitigate the effects of the considered faults. The effectiveness of the new reliability-oriented place and route algorithm is demonstrated by extensive fault injection experiments showing that the capability of tolerating SEU effects in the FPGA's configuration memory increases up to 85 times with respect to a standard TMR design technique
161Â citations
Cites background from "On the Optimal Design of Triple Mod..."
...As shown in [13], a clever selection of the TMR architecture helps in reducing the number of escaped SEUs, but it is unable to reduce them to zero....
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26 Sep 2007
TL;DR: The adoption of the triple modular redundancy coupled with the partial dynamic reconfiguration of field programmable gate arrays to mitigate the effects of soft errors in such class of device platforms is presented.
Abstract: This paper presents the adoption of the triple modular redundancy coupled with the partial dynamic reconfiguration of field programmable gate arrays to mitigate the effects of soft errors in such class of device platforms. We propose an exploration of the design space with respect to several parameters (e.g., area and recovery time) in order to select the most convenient way to apply this technique to the device under consideration. The application to a case study is presented and used to exemplify the proposed approach.
141Â citations
Cites background or methods from "On the Optimal Design of Triple Mod..."
...The adoption of the TMR as a fault mitigation technique has been proposed in recent years, such as in [3, 4], focusing the attention on the important task of the optimal design of the TMR logic (e....
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...In this scenario several studies have been carried out to deal with the problem of radiation-induced faults in SRAM-based FPGAs from different points of view ([3, 4, 5, 6, 7, 8, 9]); some of them apply well-known techniques, traditionally adopted for other platforms too, focusing the attention on the peculiarities of the selected platform, while others exploit the opportunities of reconfiguration to mitigate faults effects....
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TL;DR: A novel SEU/SET-tolerant latch called feedback redundant SEU-tolerance latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are usedto filter SETs.
Abstract: Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.
109Â citations
TL;DR: A new analytical approach is described to estimate the dependability of TMR designs implemented on SRAM-based FPGAs that is able to predict the effects of single event upsets with the same accuracy of fault injection but at a fraction of the fault-injection's execution time.
Abstract: In order to deploy successfully commercially-off-the-shelf SRAM-based FPGA devices in safety- or mission-critical applications, designers need to adopt suitable hardening techniques, as well as methods for validating the correctness of the obtained designs, as far as the system's dependability is concerned. In this paper we describe a new analytical approach to estimate the dependability of TMR designs implemented on SRAM-based FPGAs that, by exploiting a detailed knowledge of FPGAs architectures and configuration memory, is able to predict the effects of single event upsets with the same accuracy of fault injection but at a fraction of the fault-injection's execution time.
104Â citations
TL;DR: A comprehensive survey of the literature published in this rich research field during the past 10 years is provided to serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.
Abstract: The use of static random access memory (SRAM)-based field programmable gate arrays (FPGAs) in harsh radiation environments has grown in recent years. These types of programmable devices require special mitigation techniques targeting the configuration memory, the user logic, and the embedded RAM blocks. This article provides a comprehensive survey of the literature published in this rich research field during the past 10 years. Furthermore, it can also serve as a tutorial for space engineers, scientists, and decision makers who need an introduction to this topic.
98Â citations
References
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10 Sep 2001
TL;DR: In this paper, the authors present the meaningful results of a single bit upset fault injection analysis performed in Virtex FPGA triple modular redundancy (TMR) design, each programmable bit upset able to cause an error in the TMR design has been investigated.
Abstract: This paper presents the meaningful results of a single bit upset fault injection analysis performed in Virtex FPGA triple modular redundancy (TMR) design. Each programmable bit upset able to cause an error in the TMR design has been investigated. Final conclusion using the TMR "golden" comparison method shows that "no errors" were reported by Virtex TMR design implementation in the presence of single bit upsets in the customization logic. The proton radiation ground test has confirmed the results achieved by fault injection.
130Â citations
"On the Optimal Design of Triple Mod..." refers result in this paper
...Previous results from bitstream fault injection [3, 4] and radiation ground testing [5] showed that there are few upsets in the routing that can generate an error in the output....
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16 Feb 2004
TL;DR: This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory, and describes a method for obtaining the same result with similar devices.
Abstract: This paper analyses the effects of single event upsets in an SRAM-based FPGA, with special emphasis for the transient faults affecting the configuration memory. Two approaches are combined: from one side, by exploiting the available information and tools dealing with the device configuration memory, we were able to make hypothesis on the meaning of every bit in the configuration memory. From the other side, radiation testing was exploited to validate the hypothesis and to gather experimental evidence about the correctness of the obtained results. As a major result, we can provide detailed information about the effects of SEUs affecting the configuration memory of a commercial FPGA device. As a second contribution, we describe a method for obtaining the same result with similar devices. Finally, the obtained results are crucial to allow the possible usage of SRAM-based FPGAs in safety-critical environments, e.g., by working on the place and route strategies of the supporting tools.
94Â citations
"On the Optimal Design of Triple Mod..." refers methods in this paper
...The effect analysis of each faulty bitstream was done using the classification tool developed in [9]....
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12 Jul 2004
TL;DR: A fault-injection environment developed at this institution is exploited to analyze the impact of single event upsets affecting the configuration memory of SRAM-based FPGAs when fault tolerant design techniques are adopted, and shows that the TMR design technique mainly depends on the characteristics of the adopted TMR architecture in terms of placing and routing.
Abstract: The growing adoption of SRAM-based field programmable gate arrays (FPGAs) in safety-critical applications demands for efficient methodologies for evaluating their reliability. Single event upsets (SEUs) affecting the configuration memory of SRAM-based FPGAs are a major concern, since they can permanently affect the function implemented by the device. We exploited a fault-injection environment developed at our institution to analyze the impact of such faults on SRAM-based FPGAs when fault tolerant design techniques are adopted. The experimental results allow quantitative evaluations of the effects of these faults, and show that the sensitivity of the TMR design technique mainly depends on the characteristics of the adopted TMR architecture in terms of placing and routing.
61Â citations
"On the Optimal Design of Triple Mod..." refers methods in this paper
...We used a fault-injection system we developed [6] which is composed of three modules: 1....
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...To evaluate the TMR robustness a previously developed upset injection tool [6] was used to randomly inject faults in the FPGA bitstream....
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14 Apr 2004
TL;DR: The high-level method presented in this work is based on Triple Modular Redundancy and a combination of Duplication ModularRedundancy with Concurrent Error Detection (CED) techniques, which are able to cope with upsets in the combinational and in the sequential logic.
Abstract: This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable architecture, or they can be implemented at the high-level description, without modification in the FPGA architecture. The high-level method presented in this work is based on Triple Modular Redundancy (TMR) and a combination of Duplication Modular Redundancy (DMR) with Concurrent Error Detection (CED) techniques, which are able to cope with upsets in the combinational and in the sequential logic. The methodology was validated by fault injection experiments in an emulation board. Results have been analyzed in terms of reliability, input and output pin count, area and power dissipation.
47Â citations
"On the Optimal Design of Triple Mod..." refers background in this paper
...Changing the value of such a cell has a transient effect followed by a permanent effect on the controlled logic or routing [2]....
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02 Sep 2002
TL;DR: In this paper, a new fault injection environment, which offers an alternative to radiation testing for evaluating the effects of charged particles on the configuration memory of SRAM-based FPGA devices, is proposed.
Abstract: Commercial-Off-The-Shelf SRAM-based FPGA devices are becoming of interests for applications where high dependability and low cost are mandatory constraints. This paper proposes a new fault injection environment, which offers an alternative to radiation testing for evaluating the effects of charged particles on the configuration memory of SRAM-based FPGA devices. This paper describes the fault injection environment and reports preliminary results gathered on some benchmark circuits.
33Â citations