Proceedings ArticleDOI
Operating frequency improvement on FPGA implementation of a pipeline large-FFT processor
Ting-wai Siu,Chiu-Wing Sham,Francis C. M. Lau +2 more
- pp 5-9
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TLDR
Circuit complexity reduction in FPGA implementation of large N-point Radix-22 FFT with single-path delay feedback architecture is reported, and the signal critical path is reduced and the system clock frequency is increased.Abstract:
In this paper, circuit complexity reduction in FPGA implementation of large N-point Radix-22 FFT with single-path delay feedback architecture is reported. Memory requirement of the FFT in the FPGA consists of two parts, the RAM data storage of the feedback in each stage of the data flow and the twiddle factors prepared as ROM for each complex multiplication. Through address rearrangement, the ROM sizes for the twiddle factors are significantly reduced with the removal of redundancy. The reduction ratio is about 1/3(log 4 N−1). As a result, the signal critical path is reduced and the system clock frequency is increased. The proposed architecture is validated by the implementations of 1K and 4K Radix-22 FFTs in an Altera Cyclone IV FPGA, EP4CGX22, which is the second lowest capacity FPGA of the low cost series. For the 1K- and 4K-point FFTs, the operating frequencies are 231.11 MHz and 215.75 MHz, respectively, approaching 250 MHz which is the speed limit of the I/O ports of the FPGA [1].read more
Citations
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Proceedings ArticleDOI
Hardware Design and Optimization of Multimode Pipeline Based FFT for IEEE 802.11ax WLAN Devices
Phuong T.K. Dinh,Linh T.T. Dinh,Hoan V. Tran,Cuong M. Duong,Leonardo Lanante,Minh Nguyen,Hiroshi Ochi +6 more
TL;DR: To optimize the throughput and area of the FFT hardware, a new architecture of a multi-mode Fast Fourier Transform hardware for IEEE 802.11ax WLAN standard is presented and two design techniques such as compression of redundant twiddle factors, and optimization of twiddle factor multiplication are applied.
Journal ArticleDOI
Compact and high-throughput parameterisable architectures for memory-based FFT algorithms
TL;DR: This article, to the best of authors' knowledge, is the first to present a compact and yet high-throughput parameterisable hardware architecture for implementing different FFT algorithms, including Radix-2, radix-4,Radix-8, mixed-radix, and split-radIX algorithms.
Proceedings ArticleDOI
FPGA Real-time FFT Portable Core, Design and Implementation
TL;DR: A new IP core to calculate the FFT in real-time for an FPGA device that implements a radix-2 DIF for sizes of powers of two from 4 up to 65536 and uses fixed point arithmetics with a configurable number of bits and numerical format.
Book ChapterDOI
Implementation of a Pipeline Large-FFT Processor Based on the FPGA
Yongkui Ma,Henghao Liang +1 more
TL;DR: The results show that the design of the FFT processor meets the real-time requirement, and can be applied to large-point FFT computing.
Journal ArticleDOI
High performance and resource efficient FFT processor based on CORDIC algorithm
TL;DR: In this article , an improved multipath delay commutator pipelining architecture based on the radix-2 time decimation algorithm is proposed, which improves the system's computing speed and reduces the use of registers.
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Proceedings ArticleDOI
A new approach to pipeline FFT processor
Shousheng He,M. Torkelson +1 more
TL;DR: A new VLSI architecture for a real-time pipeline FFT processor is proposed, derived by integrating a twiddle factor decomposition technique in the divide-and-conquer approach, which has the same multiplicative complexity as the radix-4 algorithm, but retains the butterfly structure of the Radix-2 algorithm.
Proceedings ArticleDOI
Design and implementation of a 1024-point pipeline FFT processor
Shousheng He,M. Torkelson +1 more
TL;DR: By exploiting the spatial regularity of the new algorithm, minimal requirement for both dominant components in VLSI implementation has been achieved: only 4 complex multipliers and 1024 complex-word data memory for the pipelined 1K FFT processor.