Optical interconnects to electronic chips
TL;DR: The progress toward and prospects for the penetration of optics all the way to the silicon chip are summarized.
Abstract: Optical interconnects are progressively replacing wires at shorter and shorter distances in information processing machines. This paper summarizes the progress toward and prospects for the penetration of optics all the way to the silicon chip.
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TL;DR: An on-chip integrated wavelength demultiplexer designed using an inverse computational algorithm is experimentally demonstrated in this paper, where 1,300 and 1,550 nm wavelength light is sorted in a device area of just 2.8 µm2.
Abstract: An on-chip integrated wavelength demultiplexer designed using an inverse computational algorithm is experimentally demonstrated. 1,300 and 1,550 nm wavelength light is sorted in a device area of just 2.8 × 2.8 μm2.
817 citations
Cites background from "Optical interconnects to electronic..."
...Abstract Integrated photonic devices are poised to play a key role in a wide variety of applications, ranging from optical interconnects [1] and sensors [2] to quantum computing [3]....
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Patent•
19 Aug 2010
TL;DR: In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
Abstract: A system includes a semiconductor device. The semiconductor device includes a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single crystal silicon layer, wherein the at least one metal layer comprises copper or aluminum more than other materials; and a second single crystal silicon layer overlying the at least one metal layer. The second single crystal silicon layer comprises a plurality of second transistors arranged in substantially parallel bands. Each of a plurality of the bands comprises a portion of the second transistors along an axis in a repeating pattern.
417 citations
Patent•
28 Jun 2011
TL;DR: In this paper, a first layer and a second layer of layer-transferred mono-crystallized silicon, where the first layer comprises a first plurality of horizontally-oriented transistors, and the second layer includes a second plurality of vertically oriented transistors.
Abstract: A device comprising semiconductor memories, the device comprising: a first layer and a second layer of layer-transferred mono-crystallized silicon, wherein the first layer comprises a first plurality of horizontally-oriented transistors; wherein the second layer comprises a second plurality of horizontally-oriented transistors; and wherein the second plurality of horizontally-oriented transistors overlays the first plurality of horizontally-oriented transistors.
413 citations
Patent•
28 Mar 2011
TL;DR: In this article, a method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a metal layer overlaying the first layer and providing at least one connection to the first Transistors, and finally processing a second layer of second transistors overlaying a first metal layer, wherein the second metal layer is connected to provide power to at least 1 of the second Transistors.
Abstract: A method to process an Integrated Circuit device including processing a first layer of first transistors, then processing a first metal layer overlaying the first transistors and providing at least one connection to the first transistors, then processing a second metal layer overlaying the first metal layer, then processing a second layer of second transistors overlaying the second metal layer, wherein the second metal layer is connected to provide power to at least one of the second transistors.
351 citations
17 Aug 1989
TL;DR: In this article, the authors used three GaInAsquantum wells and diameters of several μm with room-temperature pulsed current thresholds as low as 1.3mA with 958 nm output wavelength.
Abstract: Vertical-cavity electrically driven lasers with three GaInAs
quantum wells and diameters of several μm exhibit room-temperature pulsed current thresholds as low as 1.3mA with 958 nm output wavelength.
282 citations
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TL;DR: In this article, a numerical Kramers-Kronig analysis is used to predict the refractive index perturbations produced in crystalline silicon by applied electric fields or by charge carriers.
Abstract: A numerical Kramers-Kronig analysis is used to predict the refractive-index perturbations produced in crystalline silicon by applied electric fields or by charge carriers. Results are obtained over the 1.0-2.0 \mu m optical wavelength range. The analysis makes use of experimental electroabsorption spectra and impurity-doping spectra taken from the literature. For electrorefraction at the indirect gap, we find \Delta n = 1.3 \times 10^{5} at \lambda = 1.07 \mu m when E = 10^{5} V/cm, while the Kerr effect gives \Delta n = 10^{-6} at that field strength. The charge-carrier effects are larger, and a depletion or injection of 1018carriers/cm3produces an index change of \pm1.5 \times 10^{-3} at \lambda = 1.3 \mu m.
2,502 citations
"Optical interconnects to electronic..." refers background in this paper
...Silicon-based modulators still present challenges here, though, because silicon itself only has a relatively weak mechanism (a change in refractive index with changes in carrier density) for such modulators [31]....
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...It does have a relatively weak but usable change in refractive index with carrier density, whose physics was characterized in the late 1980s [31]....
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10 Jun 2009
TL;DR: The current performance and future demands of interconnects to and on silicon chips are examined and the requirements for optoelectronic and optical devices are project if optics is to solve the major problems of interConnects for future high-performance silicon chips.
Abstract: We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.
1,959 citations
"Optical interconnects to electronic..." refers background in this paper
...We have discussed such devices elsewhere [7], and will not repeat the details here....
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...Considerations of power dissipation, bytes per FLOP, free-space optics, waveguide optics, and the resulting requirements on future optical and optoelectronic devices for interconnects are discussed in [7]....
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...For the densest future interconnects, or for direct “chip-to-network” connections for longer distances, wavelength division multiplexing may be required for waveguide systems [7]....
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...[7] for a discussion of these energies....
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...(Interestingly, these apparently also obey [7] the scaling of Eq....
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TL;DR: Detailed calculations of the shift of exciton peaks are presented including (i) exact solutions for single particles in infinite wells, (ii) tunneling resonance calculations for finite wells, and (iii) variational calculations ofexciton binding energy in a field.
Abstract: We report experiments and theory on the effects of electric fields on the optical absorption near the band edge in GaAs/AlGaAs quantum-well structures. We find distinct physical effects for fields parallel and perpendicular to the quantum-well layers. In both cases, we observe large changes in the absorption near the exciton peaks. In the parallel-field case, the excitons broaden with field, disappearing at fields \ensuremath{\sim}${10}^{4}$ V/cm; this behavior is in qualitative agreement with previous theory and in order-of-magnitude agreement with direct theoretical calculations of field ionization rates reported in this paper. This behavior is also qualitatively similar to that seen with three-dimensional semiconductors. For the perpendicular-field case, we see shifts of the exciton peaks to lower energies by up to 2.5 times the zero-field binding energy with the excitons remaining resolved at up to \ensuremath{\sim}${10}^{5}$ V/cm: This behavior is qualitatively different from that of bulk semiconductors and is explained through a mechanism previously briefly described by us [D. A. B. Miller et al., Phys. Rev. Lett. 53, 2173 (1984)] called the quantum-confined Stark effect. In this mechanism the quantum confinement of carriers inhibits the exciton field ionization. To support this mechanism we present detailed calculations of the shift of exciton peaks including (i) exact solutions for single particles in infinite wells, (ii) tunneling resonance calculations for finite wells, and (iii) variational calculations of exciton binding energy in a field. We also calculate the tunneling lifetimes of particles in the wells to check the inhibition of field ionization. The calculations are performed using both the 85:15 split of band-gap discontinuity between conduction and valence bands and the recently proposed 57:43 split. Although the detailed calculations differ in the two cases, the overall shift of the exciton peaks is not very sensitive to split ratio. We find excellent agreement with experiment with no fitted parameters.
1,731 citations
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TL;DR: Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays, which is good news since these "local" wires dominate chip wiring.
Abstract: Concern about the performance of wires wires in scaled technologies has led to research exploring other communication methods. This paper examines wire and gate delays as technologies migrate from 0.18-/spl mu/m to 0.035-/spl mu/m feature sizes to better understand the magnitude of the the wiring problem. Wires that shorten in length as technologies scale have delays that either track gate delays or grow slowly relative to gate delays. This result is good news since these "local" wires dominate chip wiring. Despite this scaling of local wire performance, computer-aided design (CAD) tools must still become move sophisticated in dealing with these wires. Under scaling, the total number of wires grows exponentially, so CAD tools will need to handle an ever-growing percentage of all the wires in order to keep designer workloads constant. Global wires present a more serious problem to designers. These are wires that do not scale in length since they communicate signals across the chip. The delay of these wives will remain constant if repeaters are used meaning that relative to gate delays, their delays scale upwards. These increased delays for global communication will drive architectures toward modular designs with explicit global latency mechanisms.
1,486 citations
"Optical interconnects to electronic..." refers background in this paper
...The analysis of the limitations of wires on chips was expanded and clarified [10]....
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Journal Article•
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TL;DR: The silicon chip has been the mainstay of the electronics industry for the last 40 years and has revolutionized the way the world operates as mentioned in this paper, however, any optical solution must be based on low-cost technologies if it is to be applied to the mass market.
Abstract: The silicon chip has been the mainstay of the electronics industry for the last 40 years and has revolutionized the way the world operates. Today, a silicon chip the size of a fingernail contains nearly 1 billion transistors and has the computing power that only a decade ago would take up an entire room of servers. As the relentless pursuit of Moore's law continues, and Internet-based communication continues to grow, the bandwidth demands needed to feed these devices will continue to increase and push the limits of copper-based signaling technologies. These signaling limitations will necessitate optical-based solutions. However, any optical solution must be based on low-cost technologies if it is to be applied to the mass market. Silicon photonics, mainly based on SOI technology, has recently attracted a great deal of attention. Recent advances and breakthroughs in silicon photonic device performance have shown that silicon can be considered a material onto which one can build optical devices. While significant efforts are needed to improve device performance and commercialize these technologies, progress is moving at a rapid rate. More research in the area of integration, both photonic and electronic, is needed. The future is looking bright. Silicon photonics could provide low-cost opto-electronic solutions for applications ranging from telecommunications down to chip-to-chip interconnects, as well as emerging areas such as optical sensing technology and biomedical applications. The ability to utilize existing CMOS infrastructure and manufacture these silicon photonic devices in the same facilities that today produce electronics could enable low-cost optical devices, and in the future, revolutionize optical communications
1,479 citations