Optimal algorithms for bubble sort based non-Manhattan channel routing
01 May 1994-IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (IEEE)-Vol. 13, Iss: 5, pp 603-609
TL;DR: A significant improvement in time complexity over the existing algorithm (which produces the best results so far) is achieved, while ensuring optimality.
Abstract: It has been pointed out that, in many cases, results generated by non-Manhattan channel routers will be better than those generated by Manhattan routers. Non-optimal bubble sort based algorithms for non-Manhattan channel routing have been proposed in the literature by also allowing connections in the +45/spl deg/ and /spl minus/45/spl deg/ directions. In this paper, optimal algorithms are proposed for the two-layer and three-layer non-Manhattan channel routing problems based on an identical problem formulation. The time complexities of our algorithms and the existing algorithm (which produces the best results so far) are O(K/sup 2/ * N) and O(K * N/sup 2/), respectively, where N is the number of terminals (i.e., the length) of the channel and N is the number of routing tracks (i.e., the height) in the channel. K is always less than N, and in most cases is much smaller than N. Clearly, a significant improvement in time complexity over the existing algorithm (which produces the best results so far) is achieved, while ensuring optimality. >
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Patent•
31 Dec 2002
TL;DR: In this paper, the shape of interconnect-line ends is dynamically defined on a particular layer based on the routing directions available on the particular layer to improve the alignment of route segments that have differing widths.
Abstract: Some embodiments of the invention provide a router that can define a route that has different widths along different directions on the same layer. To facilitate the creation of such a route, some embodiments adaptively define the shape of interconnect-line ends (i.e., the shape of route-segment ends) on a particular layer based on the routing directions available on the particular layer. By so defining these shapes, these embodiments improve the alignment of route segments that have differing widths. In other words, dynamically defining the interconnect-line ends improves the shape of a route at bends along which the route transition from one width to another. Also, to facilitate the creation of a route with different widths and/or spacing in different directions on a particular layer, some embodiments define, for each available routing direction on the particular layer, an “unroutable” bloated region about a previously defined geometry (e.g., a previously defined obstacle, wire, or via pad) on the particular layer. An item's bloated region for a particular routing direction specifies the portion of the particular layer that is not available for route segments along the particular routing direction. As further described below, the item's bloated region for a particular direction is derived based on the minimum spacing required between the item and any route segment in the particular direction for the particular net.
93 citations
Patent•
05 Jan 2002
TL;DR: In this paper, the authors proposed a routing method that uses diagonal routes to route several nets within a region of a circuit layout, each net includes a set of pins in the region, and then identifies a route that connects the sub-regions that contain a pin from the set of nets of the particular net.
Abstract: The invention is directed towards routing method and apparatus. Some embodiments provide a routing that uses diagonal routes. This method routes several nets within a region of a circuit layout. Each net includes a set of pins in the region. The method initially partitions the region into several sub-regions. For each particular net in the region, the method then identifies a route that connects the sub-regions that contains a pin from the set of pins of the particular net. Some of the identified routes have edges that are at least partially diagonal.
79 citations
TL;DR: A comprehensive review on state-of-the-art photovoltaic array reconfiguration methods through a thoroughly investigation of 125 recently published papers makes a more exhaustive classification, in which sixty-four methods are thoroughly categorized into nine groups.
71 citations
09 Nov 2003
TL;DR: In-depth analysis of deployment issues associated with the Y architecture is given, and communication capability (throughput of meshes) for different interconnect architectures is analyzed using a multicommodity flow approach and a Rentian communication model.
Abstract: The Y architecture for on-chip interconnect is based on pervasive use of 0/spl deg/, 120/spl deg/, and 240/spl deg/ oriented semiglobal and global wiring. Its use of three uniform directions exploits on-chip routing resources more efficiently than traditional Manhattan wiring architecture. This paper gives in-depth analysis of deployment issues associated with the Y architecture. Our contributions are as follows. 1) We analyze communication capability (throughput of meshes) for different interconnect architectures using a multicommodity flow approach and a Rentian communication model. Throughput of the Y architecture is largely improved compared to the Manhattan architecture, and is close to the throughput of the X architecture. 2) We improve existing estimates for the wirelength reduction of various interconnect architectures by taking into account the effect of routing-geometry-aware placement. 3) We propose a symmetrical Y clock tree structure with better total wire length compared to both H and X clock tree structures, and better path length compared to the H tree. 4) We discuss power distribution under the Y architecture, and give analytical and SPICE simulation results showing that the power network in Y architecture can achieve (8.5%) less IR drop than an equally resourced power network in Manhattan architecture. 5) We propose the use of via tunnels and banks of via tunnels as a technique for improving routability for Manhattan and Y architectures.
60 citations
Patent•
26 Aug 2002TL;DR: In this paper, the authors propose a method of routing nets in a multi-layer integrated-circuit (IC) layout, where the spacing between at least one particular route and an item adjacent to the route in the layout is different in different directions on the same layer.
Abstract: Some embodiments of the invention provide a method of routing nets in a multi-layer integrated-circuit (“IC”) layout. For each particular net in a set of nets, the method specifies different spacing constraints for routing the particular net in different directions on the same layer. It then defines a particular route for each particular net in the set of nets, where the spacing between at least one particular route and an item adjacent to the route in the layout is different in the different directions on the same layer.
59 citations
References
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28 Jun 1971
TL;DR: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards based on the newly developed channel assignment algorithm and requires many via holes.
Abstract: The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.
655 citations
TL;DR: Two new algorithms merge nets instead of assigning horizontal tracks to individual nets to route a specified net list between two rows of terminals across a two-layer channel in the layout design of LSI chips.
Abstract: In the layout design of LSI chips, channel routing is one of the key problems. The problem is to route a specified net list between two rows of terminals across a two-layer channel. Nets are routed with horizontal segments on one layer and vertical segments on the other. Connections between two layers are made through via holes. Two new algorithms are proposed. These algorithms merge nets instead of assigning horizontal tracks to individual nets. The algorithms were coded in Fortran and implemented on a VAX 11/780 computer. Experimental results are quite encouraging. Both programs generated optimal solutions in 6 out of 8 cases, using examples in previously published papers. The computation times of the algorithms for a typical channel (300 terminals, 70 nets) are 1.0 and 2.1 s, respectively.
539 citations
28 Jun 1976
TL;DR: The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer.
Abstract: This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were typical.
364 citations
01 Jan 1982
TL;DR: A new, “greedy”, channel-router that always succeeds, usually using no more than one track more than required by channel density, and may be forced in rare cases to make a few connections "off the end” of the channel.
Abstract: We present a new, "greedy", channel-router that is quick, simple, and highly effective. It always succeeds, usually using no more than one track more than required by channel density. (It may be forced in rare cases to make a few connections "off the end" of the channel, in order to succeed.) It assumes that all pins and wiring lie on a common grid, and that vertical wires are on one layer, horizontal on another. The greedy router wires up the channel in a left-to-right, column-by-column manner, wiring each column completely before starting the next. Within each column the router tries to maximize the utility of the wiring produced, using simple, "greedy" heuristics. It may place a net on more than one track for a few columns, and "collapse" the net to a single track later on, using a vertical jog. It may also use a jog to move a net to a track closer to its pin in some future column. The router may occasionally add a new track to the channel, to avoid "getting stuck".
291 citations
27 Jun 1983
TL;DR: A new channel routing algorithm is presented, based on reduction of the problem to the case of a (2 x n) grid and on consistent utilization of a "divide and conquer" approach, which consistently outperforms several known routers in quality of wiring.
Abstract: The channel routing problem is a special care of the wire routing problem when interconnections have to be performed within a rectangular strip having no obstructions, between terminals located on opposite sides of the rectangle. We present here a new channel routing algorithm, based on reduction of the problem to the case of a (2 x n) grid and on consistent utilization of a "divide and conquer" approach. For the current implementation of the algorithm, the running time is proportional to N x n x log (m), where N is the number of nets, n is the length of the channel (number of columns) and m is the width of the channel (number of tracks). Traditional technological restrictions are assumed, i.e. net terminals are located on vertical grid lines, two wiring layers are available for interconnections - one layer is used exclusively for vertical segments, another for horizontal and vias are introduced for each layer change. This algorithm consistently outperforms several known routers in quality of wiring. We tested the algorithm on several benchmark problems. One of them - Deutsch's "difficult example" - was routed with only 19 horizontal wiring tracks (the absolute minimum for this case), whereas all other known routers required 20 or more tracks.
116 citations