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Proceedings ArticleDOI

Optimal utilization of low voltage GaN HEMT in high frequency boost converter

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TLDR
In this article, an analytical loss model of GaN HEMT, in which influences of circuit and package parasitics are accounted for, is developed as a tool to analyze losses in GaNHEMT in different switching conditions.
Abstract
In this paper, investigations on optimal topology and operation mode for low voltage GaN HEMT are performed. Analytical loss model of GaN HEMT, in which influences of circuit and package parasitics are accounted for, is developed as a tool to analyze losses in GaN HEMT in different switching conditions. Analysis results shows that when applied in both V out in and V out > 2V in situations in Boundary Conduction Mode with Valley Switching(BCM-VS) in a boost converter, where GaN HEMT is switched on when voltage across it is lowered, switching loss can be greatly reduced. Switching loss reduction results not only from the exemption of discharging the large output capacitance of GaN HEMT at high voltage, but also from the fact that parasitic inductance has much less effects on switching loss in GaN HEMT in BCM-VS than in Continuous Conduction Mode (CCM). Limitations and design tradeoffs when GaN HEMT is applied in BCM-VS are also revealed. Forward voltage of GaN HEMT in reverse conduction is high and its conduction should be prevented when V out > 2V in to achieve conduction loss reduction. This further loss reduction can be realized by switching on transistor before valley point. Besides, in BCM-VS, overvoltage on GaN HEMT is larger and oscillatory energy dissipation in circuit is higher than in CCM due to higher turn off current. Paralleling external capacitor to the transistor helps to ease voltage stress; however turn on loss will be increased. This loss increase is more severe in the case of V out in than V out > 2V in . Trade-offs on the selection of proper external capacitor value exists between increased switching loss and reduced voltage stress. Experimental setup is built to verify and demonstrate the analysis.

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Citations
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Synchronous Boost Converter with GaN Switches for Photovoltaic Microconverter First Test Results

TL;DR: In this paper, the authors describe a design of MPPT converter power part prototype: modelling and experimental results, including voltage, current curves and efficiency of real prototype are compared to the results of simulations.
Proceedings ArticleDOI

Synchronous boost converter with GaN switches for photovoltaic microconverter

TL;DR: In this paper, the authors describe a design of MPPT converter power part prototype: modelling and experimental results, including voltage, current curves and efficiency of real prototype are compared to the results of simulations.

Electromagnetic Design of High Frequency PFC Boost Converters using Gallium Nitride Devices

W. Wang
TL;DR: In this paper, the authors explore high frequency operation potentials of single-die, normally-off GaN power semiconductors that are suited for high voltage, low current applications.
References
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Analytical loss model of power MOSFET

TL;DR: In this article, an accurate analytical model is proposed to calculate the power loss of a metal-oxide semiconductor field effect transistor (FET) by considering the nonlinearity of the capacitors and the parasitic inductance in the circuit, such as the source inductor shared by the power stage and driver loop, the drain inductor, etc.
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Characterization and Experimental Assessment of the Effects of Parasitic Elements on the MOSFET Switching Performance

TL;DR: In this paper, a circuit-level analytical model that takes MOSFET parasitic capacitances and inductances, circuit stray inductances and reverse current of the freewheeling diode into consideration is given to evaluate the switching characteristics.
Proceedings ArticleDOI

Experimental parametric study of the parasitic inductance influence on MOSFET switching characteristics

TL;DR: A guideline has been established for the layout and design of high-speed switching circuits based on the results obtained in an experimental parametric study of the parasitic waveform ringing, switching loss, device stress, and electromagnetic interference.
Journal ArticleDOI

Effect of Valley Switching and Switching-Frequency Limitation on Line-Current Distortions of DCM/CCM Boundary Boost PFC Converters

TL;DR: In this paper, a systematic analysis of line-current distortions of the discontinuous-conduction-mode and the continuousconductionmode boundary boost power factor correction converter due to valley switching (VS) and switching-frequency limitation, where VS is either maintained or lost after the onset of switching frequency limitation, is provided.
Proceedings ArticleDOI

Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics

TL;DR: In this article, the impact of interconnection parasitic inductance on MOSFET switching characteristics is modeled analytically and evaluated experimentally, and closed-form analytical equations are derived to evaluate switching characteristics due to common source inductance and switching loop inductance.
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