Optimization of cross-sectional aspect ratio of ballistic Si nanobar MOSFETs for superior current-voltage characteristics
15 Oct 2012-Vol. 8549, pp 409-414
TL;DR: In this paper, the carrier transport in ballistic Si-NBFETs is modeled by constructing a relevant Hamitonian matrix, where the coupling of source and drain with the channel is incorporated by the corresponding self-energy matrices.
Abstract: Si nanobar field effect transistors (Si-NBFETs) have emerged as one of the potential candidates in the present era of
nano-structured electronic devices. In the current work, the carrier transport in ballistic Si-NBFETs is modeled by
constructing a relevant Hamitonian matrix, where the coupling of source and drain with the channel is incorporated by
the corresponding self-energy matrices. The Hamiltonian is solved by non-equilibrium Green’s function formalism. The
current-voltage characteristics for different width and thickness of the nanobar channel are investigated in detail.
Comparative study on drive current and leakage current for various transverse dimensions suggests a cross-sectional
design window with an aspect ratio in the range of 1.3-1.6 to be appropriate for superior performance.
References
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TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Abstract: Silicon nanowires can be prepared with single-crystal structures, diameters as small as several nanometers and controllable hole and electron doping, and thus represent powerful building blocks for nanoelectronics devices such as field effect transistors. To explore the potential limits of silicon nanowire transistors, we have examined the influence of source-drain contact thermal annealing and surface passivation on key transistor properties. Thermal annealing and passivation of oxide defects using chemical modification were found to increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V‚s with peak values of 2000 nS and 1350 cm 2 /V‚s, respectively. The comparison of these results and other key parameters with state-of-the-art planar silicon devices shows substantial advantages for silicon nanowires. The uses of nanowires as building blocks for future nanoelectronics are discussed.
2,157 citations
"Optimization of cross-sectional asp..." refers background in this paper
...Several non-classical architectures such as double-gate (DG), triple-gate (TG), gate all-around (GAA) and nanowire MOSFETs are being explored as potential solution to meet these challenges [3-7]....
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TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Abstract: MOSFETs with gate length down to 17 nm are reported To suppress the short channel effect, a novel self-aligned double-gate MOSFET, FinFET, is proposed By using boron-doped Si/sub 04/Ge/sub 06/ as a gate material, the desired threshold voltage was achieved for the ultrathin body device The quasiplanar nature of this new variant of the vertical double-gate MOSFETs can be fabricated relatively easily using the conventional planar MOSFET process technologies
1,668 citations
"Optimization of cross-sectional asp..." refers background in this paper
...Several non-classical architectures such as double-gate (DG), triple-gate (TG), gate all-around (GAA) and nanowire MOSFETs are being explored as potential solution to meet these challenges [3-7]....
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TL;DR: The non-equilibrium Green's function (NEGF) formalism provides a sound conceptual basis for the devlopment of atomic-level quantum mechanical simulators that will be needed for nanoscale devices of the future as discussed by the authors.
Abstract: The non-equilibrium Green’s function (NEGF) formalism provides a sound conceptual basis for the devlopment of atomic-level quantum mechanical simulators that will be needed for nanoscale devices of the future. However, this formalism is based on concepts that are unfamiliar to most device physicists and chemists and as such remains relatively obscure. In this paper we try to achieve two objectives: (1) explain the central concepts that define the ‘language’ of quantum transport, and (2) illustrate the NEGF formalism with simple examples that interested readers can easily duplicate on their PCs. These examples all involve a short n + + – n + – n + + resistor whose physics is easily understood. However, the basic formulation is quite general and can even be applied to something as different as a nanotube or a molecular wire, once a suitable Hamiltonian has been identified. These examples also underscore the importance of performing self-consistent calculations that include the Poisson equation. The I–V characteristics of nanoscale structures is determined by an interesting interplay between twentieth century physics (quantum transport) and nineteenth century physics (electrostatics) and there is a tendency to emphasize one or the other depending on one’s background. However, it is important to do justice to both aspects in order to derive real insights.
1,094 citations
"Optimization of cross-sectional asp..." refers methods in this paper
...Coupling of the nanobar channel with source and drain contacts is obtained by modifying the Hamiltonian matrix through the incorporation of the corresponding self-energies ( ) D S ∑ ∑ , [8]....
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...Non-equilibrium Green’s function (NEGF) model has been emerged as the potential method to solve the problem [8, 9]....
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...MODELING OF TRANSPORT To model the electronic transport in Silicon Nanobar Field-Effect-Transistors (Si NBFET) within ballistic limit, the nanobar channel is represented by a Hamiltonian matrix coupled to the source and drain with open boundary conditions [8, 9]....
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TL;DR: A generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown nanowires is described, and a first electrical characterization proving the feasibility of the process developed and the basic functionality of this device is presented.
Abstract: Semiconducting nanowires have recently attracted considerable attention. With their unique electrical and optical properties, they offer interesting perspectives for basic research as well as for technology. A variety of technical applications, such as nanowires as parts of sensors, and electronic and photonic devices have already been demonstrated. In particular, electronic applications come more and more into focus, as the ongoing miniaturization in microelectronics demands new innovative solutions. Semiconducting nanowires, in particular epitaxially grown silicon (Si) nanowires, are considered as promising candidates for post-CMOS (CMOS: complementary metal–oxide semiconductor) logic elements owing to their potential compatibility with existing CMOS technology. One major advantage of vapor–liquid– solid(VLS-) grown nanowires compared to top-down fabricated devices is that they have well-defined surfaces. This reduces surface scattering, an issue which becomes important for devices on the nanoscale. Moreover, epitaxially grown nanowires circumvent the problem of handling and positioning nanometer-sized objects that arises in the conventional pick-and-place approach, where devices are fabricated by manipulating horizontally lying VLS-grown nanowires. The first step towards a technical realization of a nanowire logic element is the design and manufacturing of a nanowire transistor. The epitaxial growth of vertical nanowires offers advantages over other approaches: For example, the transistor gate can be wrapped around the vertically oriented nanowire. Such a wrapped-around gate allows better electrostatic gate control of the conducting channel and offers the potential to drive more current per device area than is possible in a conventional planar architecture. In this Communication, a generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown nanowires is described. Exemplarily, we used Si nanowires and present a first electrical characterization proving the feasibility of the process developed and the basic functionality of this device. Figure 1a shows a schematic cross section through a conventional p-type MOSFET. In such a device, an inversion channel can be created close to the gate by applying a negative gate voltage. This forms a conducting channel that connects the p-doped regions between the source and drain contacts electrically. Using this concept, a silicon nanowire VS-FET would ideally require a nanowire that is n-doped in the region of the gate and p-doped elsewhere. Unfortunately, such a p-n-p structure with abrupt transitions appears difficult to realize if the nanowires are grown by means of the vapor–liquid–solid mechanism using gold as a catalyst. The difficulty here is that the dopant atoms, which are dissolved in the catalyst droplet, might act as a reservoir, thus creating a graded transition when switching to another dopant. Therefore, we used a structure consisting of an n-doped silicon nanowire grown on a p-type substrate (see Figure 1b). If the gate–drain and gate–source distances are not too long, it is electrostatically still possible to create an inversion channel along the length of the entire wire. In the proposed configuration, the p–n junction at the source contact (Figure 1a) is replaced by a Au/n-Si Schottky contact at the nanowire tip. In order to investigate the influence of the Au/n-Si Schottky contact on the nanowire (current–voltage) I–V characteristics, an array of n-doped nanowires vertically grown on an n-type (111)-oriented substrate was imbedded in a spin-coated SiO2 matrix. After removing the thin SiO2 coverage from the Au tips by a short reactive ion etching, contacts 0.6 mm in size were defined by evaporating aluminum onto the sample, such that approximately 10 nanowires were contacted in parallel. The temperature-dependent measurements (shown in Figure 2) were performed by applying a voltage to the Si substrate, while the Al top contact was held at a constant potential. The measurements reveal a strong rectifying behavior with a thermally activated current possessing an activation energy of 0.6 eV. This can be explained by the Au/n-Si Schottky contact dominating the I–V behavior. The fact that the Schottky contact is forward-biased for negative voltages furthermore proves that, as expected, electrons act as majority charge carries. Figure 1. Schematics of a) a conventional p-channel MOSFET and b) a silicon nanowire vertical surround-gate field-effect transistor.
419 citations
"Optimization of cross-sectional asp..." refers background in this paper
...Several non-classical architectures such as double-gate (DG), triple-gate (TG), gate all-around (GAA) and nanowire MOSFETs are being explored as potential solution to meet these challenges [3-7]....
[...]
TL;DR: In this article, a 3D quantum simulator for the silicon nanowire transistor (SNWT) is presented, where the authors use Buttiker probes to simulate the effects of scattering on both internal device characteristics and terminal currents.
Abstract: The silicon nanowire transistor (SNWT) is a promising device structure for future integrated circuits, and simulations will be important for understanding its device physics and assessing its ultimate performance limits. In this work, we present a three-dimensional (3D) quantum mechanical simulation approach to treat various SNWTs within the effective-mass approximation. We begin by assuming ballistic transport, which gives the upper performance limit of the devices. The use of a mode space approach (either coupled or uncoupled) produces high computational efficiency that makes our 3D quantum simulator practical for extensive device simulation and design. Scattering in SNWTs is then treated by a simple model that uses so-called Buttiker probes, which was previously used in metal-oxide-semiconductor field effect transistor simulations. Using this simple approach, the effects of scattering on both internal device characteristics and terminal currents can be examined, which enables our simulator to be used f...
351 citations