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Proceedings ArticleDOI

Optimization of cross-sectional aspect ratio of ballistic Si nanobar MOSFETs for superior current-voltage characteristics

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TLDR
In this paper, the carrier transport in ballistic Si-NBFETs is modeled by constructing a relevant Hamitonian matrix, where the coupling of source and drain with the channel is incorporated by the corresponding self-energy matrices.
Abstract
Si nanobar field effect transistors (Si-NBFETs) have emerged as one of the potential candidates in the present era of nano-structured electronic devices. In the current work, the carrier transport in ballistic Si-NBFETs is modeled by constructing a relevant Hamitonian matrix, where the coupling of source and drain with the channel is incorporated by the corresponding self-energy matrices. The Hamiltonian is solved by non-equilibrium Green’s function formalism. The current-voltage characteristics for different width and thickness of the nanobar channel are investigated in detail. Comparative study on drive current and leakage current for various transverse dimensions suggests a cross-sectional design window with an aspect ratio in the range of 1.3-1.6 to be appropriate for superior performance.

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References
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Journal ArticleDOI

High Performance Silicon Nanowire Field Effect Transistors

TL;DR: In this article, the influence of source-drain contact thermal annealing and surface passivation on key transistor properties was examined, and it was shown that thermal annaling and passivation of oxide defects using chemical modification can increase the average transconductance from 45 to 800 nS and average mobility from 30 to 560 cm 2 /V
Journal ArticleDOI

FinFET-a self-aligned double-gate MOSFET scalable to 20 nm

TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Journal ArticleDOI

Nanoscale device modeling: the Green’s function method

TL;DR: The non-equilibrium Green's function (NEGF) formalism provides a sound conceptual basis for the devlopment of atomic-level quantum mechanical simulators that will be needed for nanoscale devices of the future as discussed by the authors.
Journal ArticleDOI

Realization of a silicon nanowire vertical surround-gate field-effect transistor.

TL;DR: A generic process for fabricating a vertical surround-gate field-effect transistor (VS-FET) based on epitaxially grown nanowires is described, and a first electrical characterization proving the feasibility of the process developed and the basic functionality of this device is presented.
Journal ArticleDOI

A three-dimensional quantum simulation of silicon nanowire transistors with the effective-mass approximation

TL;DR: In this article, a 3D quantum simulator for the silicon nanowire transistor (SNWT) is presented, where the authors use Buttiker probes to simulate the effects of scattering on both internal device characteristics and terminal currents.
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