Optimization of hybrid final adder for the high performance multiplier
26 Jul 2012-pp 1-6
TL;DR: This work derives some mathematical expressions to find the size of different regions in the partial product arrival profile which helps to design optimal adder for each region in HPM based parallel multiplier.
Abstract: In this work we evaluated arrival profile of the HPM based multiplier partial products reduction tree in two ways: 1.manual delay, area calculation through logical effort, 2.ASIC implementation. Based on the arrival profile, we worked with some recently proposed optimal adders and finally we proposed an optimal hybrid adder for the final addition in HPM based parallel multiplier. This work derives some mathematical expressions to find the size of different regions in the partial product arrival profile which helps to design optimal adder for each region. This work evaluates the performance of proposed hybrid adder in terms of area, power and delay using 90nm technology. This work deals with manual calculation for 8-b and ASIC simulation of different adder designs for 8-b, 16-b, 32-b and 64-b multiplier bit sizes.
Citations
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TL;DR: The comparative analysis of all the design for the delay, area foot print and energy has done using Cadence 180nm RTL complier to show that Baugh Wooley multiplier can become more faster than the Modified Booth Multiplier.
Abstract: Modified Booth Multiplier is one of the different techniques for signed multiplication. It is used normally as the fastest multiplier. Baugh Wooley Multiplier is another technique for signed multiplication. It is not widely used because of its complexity of its structure. Here design and implementation of 8 bit Modified Booth multiplier and Baugh Wooley multiplier has done using conventional method as well as using High Performance Multiplier Reduction tree (HPM) technique. The comparative analysis of all the design for the delay, area foot print and energy has done using Cadence 180nm RTL complier to show that Baugh Wooley multiplier can become more faster than the Modified Booth Multiplier.
8 citations
References
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TL;DR: This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA, and develops and compared with the regular SQRT C SLA architecture.
Abstract: Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient gate-level modification to significantly reduce the area and power of the CSLA. Based on this modification 8-, 16-, 32-, and 64-b square-root CSLA (SQRT CSLA) architecture have been developed and compared with the regular SQRT CSLA architecture. The proposed design has reduced area and power as compared with the regular SQRT CSLA with only a slight increase in the delay. This work evaluates the performance of the proposed designs in terms of delay, area, power, and their products by hand with logical effort and through custom design and layout in 0.18-μm CMOS process technology. The results analysis shows that the proposed CSLA structure is better than the regular SQRT CSLA.
377 citations
TL;DR: The proposed method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known, and it is easy to incorporate this method in silicon compilation or logic synthesis tools.
Abstract: This paper presents a method and an algorithm for generation of a parallel multiplier, which is optimized for speed. This method is applicable to any multiplier size and adaptable to any technology for which speed parameters are known. Most importantly, it is easy to incorporate this method in silicon compilation or logic synthesis tools. The parallel multiplier produced by the proposed method outperforms other schemes used for comparison in our experiment. It uses the minimal number of cells in the partial product reduction tree. These findings are tested on design examples simulated in 1 /spl mu/ CMOS ASIC technology.
370 citations
"Optimization of hybrid final adder ..." refers methods in this paper
...It is claimed by [11] that HPM gives minimal multiplier delay due to systematic sizing of logic circuitry, and it is claimed as faster and power efficient compared to normal Dadda, Wallace and TDM multiplier [12]....
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TL;DR: A new modified Booth encoding (MBE) scheme is proposed to improve the performance of traditional MBE schemes and a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA).
Abstract: This paper presents a design methodology for high-speed Booth encoded parallel multiplier. For partial product generation, we propose a new modified Booth encoding (MBE) scheme to improve the performance of traditional MBE schemes. For final addition, a new algorithm is developed to construct multiple-level conditional-sum adder (MLCSMA). The proposed algorithm can optimize final adder according to the given cell properties and input delay profile. Compared with a binary tree-based conditional-sum adder, the speed performance improvement is up to 25 percent. On average, the design developed herein reduces the total delay by 8 percent for parallel multiplier. The whole design has been verified by gate level simulation.
263 citations
"Optimization of hybrid final adder ..." refers background in this paper
...The hybrid adder concept has been discussed earlier [1]-[3]....
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23 May 2005
TL;DR: An area efficient square root CSL scheme based on a new first zero detection logic is proposed that witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique.
Abstract: The carry-select method has deemed to be a good compromise between cost and performance in carry propagation adder design. However, the conventional carry-select adder (CSL) is still area-consuming due to the dual ripple-carry adder structure. The excessive area overhead makes CSL relatively unattractive but this has been circumvented by the use of an add-one circuit introduced recently. In this paper, an area efficient square root CSL scheme based on a new first zero detection logic is proposed. The proposed CSL witnesses a notable power-delay and area-delay performance improvement by virtue of proper exploitation of logic structure and circuit technique. For 64-bit addition, our proposed CSL requires 44% fewer transistors than the conventional one. Simulation results indicate that our proposed CSL can complete 64-bit addition in 1.50 ns and dissipate only 0.35 mW at 1.8V in TSMC 0.18 /spl mu/m CMOS technology.
196 citations
TL;DR: Improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile are discussed, yielding a faster multiplier.
Abstract: In this paper we discuss improvements in bit reduction techniques in a parallel multiplier and the use of a final adder which is optimized for the uneven signal arrival profile. Different architectures of the column compressors and the use of carry propagate adders which take advantage of the speed of the carry signal are considered. The column compressors configuration is optimized in order to reduce the longest signal path. The final adder is designed for the uneven input arrival time of the signals originating from the multiplier tree. This results in more compact wiring and balanced delays yielding a faster multiplier. >
129 citations