Proceedings ArticleDOI
Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET
Vandna Sikarwar,Saurabh Khandelwal,Shyam Akashe +2 more
- pp 166-170
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TLDR
The total leakage of DG FinFET SRAM cell is reduced by 34% after applying self controllable voltage level technique and the sub-threshold leakage current and gate leakage current of internal transistors are observed.Abstract:
Scaling of conventional CMOS circuit tends to have short channel effects due to which, effect such as drain induced barrier lowering, hot electron effect, punch through etc takes place and hence leakage increases in the transistor. To minimize short channel effects, double gate FinFET is used. FinFET may be the most promising device in the LSI (large scale integration) circuits because it realizes the self-aligned double-gate structure easily. In this paper, six transistors SRAM cell is designed using the tied gate DG FinFET. Sub-threshold leakage current and gate leakage current of internal transistors are observed and compared with the conventional structure of 6T SRAM cell. DG FinFET SRAM cell is applied with self controllable voltage level technique and then leakage current is observed. Simulation is performed with cadence virtuoso tool in 45 nm technology. The total leakage of DG FinFET SRAM cell is reduced by 34% after applying self controllable voltage level technique.read more
Citations
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Journal ArticleDOI
Low-power and high-speed 13T SRAM cell using FinFETs
Shilpa Saxena,Rajesh Mehra +1 more
TL;DR: From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to theUse of transmission gates in the access path.
Journal ArticleDOI
Analysis and design of low power SRAM cell using independent gate FinFET
TL;DR: A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption.
Proceedings ArticleDOI
Low power SRAM design using independent gate FinFET at 30nm technology
TL;DR: In this article, the authors have designed SRAM cell using double gate FinFET to minimize short channel effects, they have designed 8×8 memory array using the best configuration using the Cadence virtuoso tool.
Journal ArticleDOI
Analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET)
TL;DR: In this article, an analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET) has been developed by solving 2D-Poisson equation in cylindrical coordinates.
Proceedings ArticleDOI
Performance and analysis of 10T Full Adder using MTCMOS technique
TL;DR: In this article, the performance of full adder with MTCMOS technology at 45nm technology has been analyzed for leakage current, active power, delay and noise with power supply of (0.7 V) and propagation delay of 10.24ns.
References
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Journal ArticleDOI
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits
TL;DR: Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices and different circuit techniques to reduce the leakage power consumption are explored.
Journal ArticleDOI
FinFET-a self-aligned double-gate MOSFET scalable to 20 nm
Digh Hisamoto,Wen-Chin Lee,J. Kedzierski,Hideki Takeuchi,K. Asano,C. Kuo,Erik H. Anderson,Tsu-Jae King,Jeffrey Bokor,Chenming Hu +9 more
TL;DR: In this paper, a self-aligned double-gate MOSFET, FinFET was proposed by using boron-doped Si/sub 04/Ge/sub 06/ as a gate material.
Proceedings ArticleDOI
Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length
K. Okano,Takashi Izumida,H. Kawasaki,Akio Kaneko,Atsushi Yagishita,Takahisa Kanemura,Masaki Kondo,Sanae Ito,Nobutoshi Aoki,Kiyotaka Miyano,T. Ono,K. Yahashi,K. Iwade,T. Kubota,T. Matsushita,Ichiro Mizushima,Satoshi Inaba,Kazunari Ishimaru,K. Suguro,Kazuhiro Eguchi,Y. Tsunashima,Hidemi Ishiuchi +21 more
TL;DR: In this article, a CMOS FinFET fabricated on bulk Si substrate is discussed from the viewpoint of device size scalability and short channel effect control, and a trimming technique by special oxidation was applied to reduce fin width down to sub-10 nm regime.
Journal ArticleDOI
Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs
S.A. Tawfik,Volkan Kursun +1 more
TL;DR: In this paper, the authors proposed independently biased double-gate FinFET sequential circuits to reduce the active power consumption, the clock power, the leakage power, and the circuit area.
Journal ArticleDOI
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices
TL;DR: An efficient circuit synthesis methodology comprised of proposed low-power logic options in FinFET design library has been developed and results show about 8.5% area savings and 18% power savings over conventional FinFet technology for ISCAS85 benchmark circuits in 45-nm technology with no performance penalty.
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