Optimized Substrate for Improved Performance of Stacked Nanosheet Field-Effect Transistor
TL;DR: In this article, the authors proposed SuperSteep-Retrograde silicon substrate (SSR-Si) configuration which reduces the tunneling current by increasing the tunnel barrier width and diminishing the peak electric field at the drain-substrate junction.
Abstract: The recently proposed stacked nanosheet-field-effect transistor (SNSH-FET) is considered as a promising candidate for continued scaling with silicon. While using punchthrough-stopper-doped (or) ground-plane-doped silicon substrate (PTS-Si substrate) in which the top part of the substrate is doped heavily with the p-type (for nMOS) impurity to avoid punchthrough leakage between the source and the drain. The heavily doped p–n junction formed at the drain–substrate junction acts as a reverse-biased tunnel diode during ${V}_{{\text {DS}}}$ biasing, which leads to large substrate leakage current. We presented SuperSteep-Retrograde silicon substrate (SSR-Si substrate) configuration which reduces the tunneling current by increasing the tunnel barrier width and diminishing the peak electric field at the drain–substrate junction. The SSR-Si substrate is achieved by growing a lightly doped or undoped layer of silicon (SSR-buffer layer) on the PTS-doped substrate. The impact of SSR-buffer layer thickness is studied and the optimal thickness (12 nm) is presented. The vertically stacked channels’ configuration leads to position-dependent current densities in different channels due to position-dependent series resistance. Herein, we present nanosheet width optimization as a solution to achieve homogeneous current ratio between all the channels thereby resulting in better linearity performance. The self-heating and RF performance of the presented SSR-Si substrate is compared with the silicon-on-insulator (SOI) substrate. The results show that SSR-Si substrate can be a better substrate for SNSH-FET because of better self-heating performance.
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TL;DR: It can be concluded that vertically stacked NS-FET is the most promising solution for future digital/analog integrated circuit applications due to their outstanding capability to keep Moore's Law alive.
29 citations
TL;DR: In this paper , the authors analyzed the self-heating effects of multi-nanosheet FET (mNS-FET) at the device and circuit level considering the introduction of punchthrough-stopper (PTS) doping and bottom oxide (BO), which are substrate processes to reduce leakage current.
Abstract: Self-heating effects (SHEs) of multi-nanosheet FET (mNS-FET) at the 3-nm technology node were analyzed at the device and circuit level considering the introduction of punchthrough-stopper (PTS) doping and bottom oxide (BO), which are substrate processes to reduce leakage current. Changes in the heat path according to the back-end-of-line (BEOL) configuration and package type were also considered. After optimizing the PTS doping and BO process through six case analyses using three-dimensional (3-D) TCAD simulations, SHE characteristics were investigated. As a result, the channel temperature risen due to SHE was larger when BO was applied than when BO was not applied, and that the face-down package was more effective in heat dissipation than the face-up package. Next, the SHE behavior during dynamic operation of logic and analog circuits was analyzed through SPICE modeling, and the effect of this on circuit performance and reliability was analyzed. As a result, in the logic ring oscillator circuit, the SHE shows a slight AC performance degradation of ~1.3%, but in terms of reliability, it causes a decrease in the lifetime of 15.1%–22.1%. In the two types of analog circuits, the possibility of circuit malfunction can be confirmed by SHE, and in terms of reliability, it causes a reduction in lifetime of 53.5%–89.9%. Therefore, it is expected that device and circuit design that can reduce SHE are required in consideration of the various processes analyzed in this work.
21 citations
TL;DR: In this article, the performance of stacked Si gate-all-around (GAA) nanosheet FET (NSHFET) has been investigated by adopting the metal (M0) source/drain (S/D) engineered contacts such as M0-wrap around the Si S/D epitaxial regions and M0 filling through s/D trenched regions.
Abstract: In this article, we investigate the electro-thermal (ET) performance of stacked Si gate-all-around (GAA) nanosheet FET (NSHFET) by adopting the metal (M0) source/drain (S/D) engineered contacts such as M0-wrap around the Si S/D epitaxial regions and M0 filling through S/D trenched regions in addition to the conventional scheme where metal (M0) epi on the S/D. The device ET performance is enhanced by increasing the device on-state current ( ${I_{ \mathrm{\scriptscriptstyle ON}}}$ ) by more than 10% with better device lattice heat removal from the hot-spot location of the NSHFET. This results in decreased device self-heating by lowering lattice hot-spot temperature ( ${T}_{L, max}$ ) and device effective thermal resistance ( ${R}_{th, eff}$ ) by more than 11% compared to conventional M0-epi-based NSHFET design. The junction temperature difference between the nanosheet channels is also lowered, which decreases the inter-sheet threshold voltage ( ${V}_{T}$ ) difference. The benchmarking study of the device designs reveals that M0-trench-based NSHFET gives the best performance from both electrical and thermal perspective for future sub-5-nm CMOS logic technologies.
19 citations
TL;DR: In this paper, the analog/RF performance of n-channel vertically stacked gate all around (GAA) silicon nanosheet field effect transistors (Si-NSFETs) is investigated using 3-dimensional TCAD simulations.
Abstract: In this article, the analog/RF performance of n-channel vertically stacked gate all around (GAA) silicon nanosheet field effect transistors (Si-NSFETs) are investigated using 3-D TCAD simulations The influence of gate length (LG) scaling, nanosheet width (WNS) and spacing between the nanosheets on the analog/RF performance of vertically stacked GAA Si-NSFET with two nanosheets are explored The 3-D TCAD simulations indicates that reducing LG from 20 nm to 12 nm results in the improvement of RF performance in terms of increased gm (transconductance), drive current, fT (cut off frequency), fmax (maximum oscillation frequency) and degradation of analog performance in terms of reduced intrinsic gain 3-D TCAD simulations also shows that increasing the WNS from 10 nm to 18 nm leads to the enhancement of gm and drive current, does not affect the fT and degrades the intrinsic gain due to the increase of drain conductance and gate capacitance It is also observed that the spacing between the nanosheets does not have any significant impact on analog/RF performance of vertically stacked GAA Si-NSFETs Consequently, the vertically stacked GAA Si-NSFETs with lower LG and higher WNS will be more suitable to realize both flash memory and dynamic random access memory (DRAM) for improved performance owing to their better RF performance
19 citations
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TL;DR: In this article, the scaling of fully depleted SOI devices is considered and the concept of controlling horizontal leakage through vertical structures is highlighted, and several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design.
Abstract: Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >
921 citations
"Optimized Substrate for Improved Pe..." refers background in this paper
...A similar vertical substrate doping engineering approach has been demonstrated in [5] and [6]....
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TL;DR: In this paper, a 3D simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFETs is presented.
Abstract: A three-dimensional (3-D) "atomistic" simulation study of random dopant induced threshold voltage lowering and fluctuations in sub-0.1 /spl mu/m MOSFETs is presented. For the first time a systematic analysis of random dopant effects down to an individual dopant level was carried out in 3-D on a scale sufficient to provide quantitative statistical predictions. Efficient algorithms based on a single multigrid solution of the Poisson equation followed by the solution of a simplified current continuity equation are used in the simulations. The effects of various MOSFET design parameters, including the channel length and width, oxide thickness and channel doping, on the threshold voltage lowering and fluctuations are studied using typical samples of 200 atomistically different MOSFETs. The atomistic results for the threshold voltage fluctuations were compared with two analytical models based on dopant number fluctuations. Although the analytical models predict the general trends in the threshold voltage fluctuations, they fail to describe quantitatively the magnitude of the fluctuations. The distribution of the atomistically calculated threshold voltage and its correlation with the number of dopants in the channel of the MOSFETs was analyzed based on a sample of 2500 microscopically different devices. The detailed analysis shows that the threshold voltage fluctuations are determined not only by the fluctuation in the dopant number, but also in the dopant position.
699 citations
"Optimized Substrate for Improved Pe..." refers background in this paper
...A similar vertical substrate doping engineering approach has been demonstrated in [5] and [6]....
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05 Jun 2017
TL;DR: In this paper, the authors demonstrate that horizontally stacked gate-all-around (GAA) nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond.
Abstract: In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.
547 citations
"Optimized Substrate for Improved Pe..." refers background or methods in this paper
...For model parameter calibration, the experimental data presented in [1] are used....
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...Matched transfer characteristic of simulated Type-1 SNSH-FET (NSH_W = 50 nm) with [1]....
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...using a similar flow as FinFET processing with Si/SiGe stack as reported in [1] and [2]; we modeled a similar flow in...
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01 Dec 1987
TL;DR: In this article, the gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage, due to the band-to-band tunneling occurring in the deep-depletion layer in the gateto-drain overlap region.
Abstract: Significant gate-induced drain leakage current can be detected in thin gate oxide MOSFETs at drain voltages much lower than the junction breakdown voltage. This current is found to be due to the band-to-band tunneling occurring in the deep-depletion layer in the gate-to-drain overlap region. In order to limit the leakage current to 0.1pA/µm, the oxide field in the gate-to-drain overlap region must be limited to 1.9MV/cm. This may set another constraint for the power supply voltage and/or oxide thickness in VLSI MOSFET scaling Device design considerations for minimizing the gate-induced drain leakage current are discussed.
338 citations
"Optimized Substrate for Improved Pe..." refers background in this paper
...2 V, the e-current component of ISOURCE (thermionic current) becomes constant; on the other hand, the hole current component becomes dominant which is due to gate-induced drain leakage (GIDL) [15], [16]....
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...5(b) shows the comparison of ISUB for different B_TH values with ISOURCE component, which shows that the ISUB value reduced below than ISOURCE which is due to GIDL (for B_TH thickness of 12 nm)....
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...The negative bias at the gate terminal leads to band bending at the channel which causes tunneling of the electrons from the valance band of the channel region into the conduction band of the drain region thereby leaving holes which are collected by the source and substrate terminals; this phenomenon is known as GIDL [15], [16]....
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...When VGS ≥ −0.2 V, the e-current component of ISOURCE (thermionic current) becomes constant; on the other hand, the hole current component becomes dominant which is due to gate-induced drain leakage (GIDL) [15], [16]....
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...band of the channel region into the conduction band of the drain region thereby leaving holes which are collected by the source and substrate terminals; this phenomenon is known as GIDL [15], [16]....
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