Overview of Power Integrity Solutions on Package and PCB: Decoupling and EBG Isolation
TL;DR: In this article, the authors reviewed possible solutions based on decoupling or isolation for suppressing power distribution network (PDN) noise on package or printed circuit board (PCB) levels.
Abstract: Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed.
Citations
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TL;DR: The fundamentals and latest progress of modeling, analysis, and design technologies for signal integrity and electromagnetic compatibility on PCB and package in the past decades are reviewed and the necessity of practical training of designers is mentioned.
Abstract: This paper reviews the fundamentals and latest progress of modeling, analysis, and design technologies for signal integrity and electromagnetic compatibility on PCB and package in the past decades. Most results in this field are based on the very rich and highly educational literature produced by Prof. C. Paul in his long scientific career. The inclusion of parameters variability effects is also considered, and it is demonstrated how statistical simulations can become affordable by means of recently-introduced stochastic methods. Finally, the necessity of practical training of designers is mentioned, and an experience relying on realistic PCB demonstrators is illustrated.
166 citations
TL;DR: In this paper, a closely located dual-band meander-line antenna array with isolation enhancement by inserting novel split electromagnetic bandgap (EBG) uniplanar structure is proposed.
Abstract: A closely located dual-band meander-line antenna array with isolation enhancement by inserting novel split electromagnetic bandgap (EBG) uniplanar structure is proposed. The meander-line antenna is coupled to a parasitic rectangular patch to achieve the dual-band operation. Splits are applied on the surface of an EBG structure to cause decoupling at the first resonant mode and utilizing an EBG structure to decouple at the second resonant mode. The prototype of the proposed structure achieves a dual band of 180 MHz (3.42–3.6 GHz) and 400 MHz (4.7–5.1 GHz). The mutual coupling is significantly reduced by 26 and 44 dB at 3.48 and 4.88 GHz, respectively, compared to the reference antenna. In addition, the structure has high front-to-back ratio radiation characteristics.
120 citations
Cites background from "Overview of Power Integrity Solutio..."
...The lower and upper cutoff frequencies ( fL and fU ) of the stopband can be derived from the following equations [24]:...
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TL;DR: In this paper, a dual-band, circularly polarized slot antenna with broadband characteristics in both axial ratio and impedance is developed, where the radiations of antenna exhibit a left-hand circular polarization in the z > 0 direction and a right-hand linear polarisation in the opposite direction at both the lower and upper bands.
Abstract: A novel dual-band, circularly polarized slot antenna with broadband characteristics in both axial ratio and impedance is developed. The radiations of antenna exhibit a left-hand circular polarization in the z > 0 direction and a right-hand circular polarization in the opposite direction at both the lower and upper bands. The measured impedance bandwidths are 55.33% (1.83-3.23 GHz) and 20.98% (4.99-6.16 GHz) while the axial ratio bandwidths are 32.14% (1.88-2.60 GHz) and 31.49% (4.95-6.80 GHz) at the lower and upper bands, respectively. In comparison to the recent works, the proposed antenna has a simpler structure, a more compact size, wider impedance bandwidths, and wider axial ratio bandwidths.
45 citations
TL;DR: The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer from a linear differential equation obtained from asymptotic linear inverter I-V curves.
Abstract: The transfer functions relating supply voltage fluctuations to jitter are analytically derived in closed form expressions for a single-ended buffer. The analytic transfer functions are derived from a linear differential equation obtained from asymptotic linear inverter I-V curves. The transfer functions are validated by comparison with HSPICE simulations. The estimated jitter is compared with the simulated jitter using eye diagrams with single-frequency and multitone supply voltage fluctuations.
44 citations
Additional excerpts
...high performance and reliability [2]–[5]....
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TL;DR: The ability to spatially vary a lattice in this manner enables new design paradigms that are not possible using spatial transforms, three of which are discussed here.
Abstract: Spatial transforms are a popular technique for designing periodic structures that are macroscopically inhomogeneous. The structures are often required to be anisotropic, provide a magnetic response, and to have extreme values for the constitutive parameters in Maxwell's equations. Metamaterials and photonic crystals are capable of providing these, although sometimes only approximately. The problem still remains about how to generate the geometry of the final lattice when it is functionally graded, or spatially varied. This paper describes a simple numerical technique to spatially vary any periodic structure while minimizing deformations to the unit cells that would weaken or destroy the electromagnetic properties. New developments in this algorithm are disclosed that increase efficiency, improve the quality of the lattices and provide the ability to design aplanatic metasurfaces. The ability to spatially vary a lattice in this manner enables new design paradigms that are not possible using spatial transforms, three of which are discussed here. First, spatially variant self-collimating photonic crystals are shown to flow unguided waves around very tight bends using ordinary materials with low refractive index. Second, multi-mode waveguides in spatially variant band gap materials are shown to guide waves around bends without mixing power between the modes. Third, spatially variant anisotropic materials are shown to sculpt the near-field around electric components. This can be used to improve electromagnetic compatibility between components in close proximity.
42 citations
References
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TL;DR: In this paper, the impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models.
Abstract: Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.
468 citations
TL;DR: In this paper, a novel approach for the suppression of the parallel-plate waveguide (PPW) noise in high-speed printed circuit boards is presented, where one of the two conductors forming the PPW is replaced by an electromagnetic bandgap (EBG) surface.
Abstract: A novel approach for the suppression of the parallel-plate waveguide (PPW) noise in high-speed printed circuit boards is presented. In this approach, one of the two conductors forming the PPW is replaced by an electromagnetic bandgap (EBG) surface. The main advantage of the proposed approach over the commonly practiced methods is the omnidirectional noise suppression it provides. For this purpose, two EBG structures are initially designed by utilizing an approximate circuit model. Subsequently, the corresponding band structures are characterized by analytical solutions using the transverse resonance method, as well as full-wave finite-element simulations. The designed EBG surfaces were fabricated and employed in a number of PPW test boards. The corresponding frequency-domain measurements exhibited bandgaps of approximately 2.21 and 3.35 GHz in the frequency range below 6 GHz. More importantly, suppression of the PPW noise by 53% was achieved based on time-domain reflectometry experiments, while maintaining the signal transmission quality within the required specifications for common signaling standards.
361 citations
"Overview of Power Integrity Solutio..." refers background in this paper
...The typical isolation approaches include etched slots on power or ground planes [13], [29]–[34], a π filter with beads [35], or electromagnetic bandgap (EBG) structures [36]–[57]....
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...circuits covering a wide frequency band [36]–[38], [40]–[43], [45], [48], [49]....
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...ries LC resonator formed between the power and ground planes could intuitively explain the mechanism of the PDN noise suppression [36], [37]....
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...9(a) and (b) shows two typical EBG structures of mushroom type and coplanar type, respectively [36]–[38], [40]–[43], [45], [48], [49]....
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TL;DR: The SOP package overcomes both the computing limitations and integration limitations of SOC, SIP, MCM, and traditional system packaging by having global wiring as well as RF, digital, and optical component integration in the package, not in the chip.
Abstract: In the past, microsystems packaging played two roles: 1) it provided I/O connections to and from integrated circuits (ICs) or wafer-level packaging (WLP), and 2) it interconnected both active and passive components on system level boards, referred to as systems packaging. Both were accomplished by interconnections or multilayer wiring at the package or board level. More recently, the IC devices have begun to integrate not only more and more transistors, but also active and passive components on an individual chip, leading the community to believe that someday there may be a single-chip complete system, referred to as system-on-chip (SOC). This can be called horizontal or two-dimensional (2-D) integration of IC blocks in a single-chip toward end-product systems. The community began to realize, however, that such an approach presents fundamental, engineering, and investment limits, as well as computing and communication limits for wireless and wired systems over the long run. This led to 3-D packaging approaches, often referred to as system-in-package (SIP). The SIP, while providing major opportunities in both miniaturization and integration for advanced and portable electronic products, is a subsystem, limited by the CMOS process just like the SOC. Some existing and emerging applications, however, include sensors, memory modules and embedded processors with DRAMs. More recent 3-D solutions, which incorporate stacked package approaches, offer solutions toward faster time-to-market and business impediments that have plagued MCM deployment for the past decade. There is a new emerging concept called system-on-package (SOP). With SOP, the package, not the board, is the system. As such, SOP is beginning to address the shortcomings of both SOC and SIP, as well as traditional packaging which is bulky, costly, and lower in performance and reliability than ICs, in two ways: 1) It uses CMOS-based silicon for what it is good for, namely, for transistor integration, and the package, for what it is good for, namely, RF, optical, and digital integration by means of IC-package-system codesign. The SOP package, therefore, overcomes both the computing limitations and integration limitations of SOC, SIP, MCM, and traditional system packaging. It does this by having global wiring as well as RF, digital, and optical component integration in the package, not in the chip. The SOP, therefore, includes both active and passive components in thin-film form, in contrast with indiscrete or thick-film form, including embedded digital, RF, and optical components, and functions in a microminiaturized package or board.
275 citations
"Overview of Power Integrity Solutio..." refers background in this paper
...with RF circuits, and higher throughput of data communication [5]....
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Book•
19 Nov 2007
TL;DR: This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists.
Abstract: The First Comprehensive, Example-Rich Guide to Power Integrity ModelingProfessionals such as signal integrity engineers, package designers, and system architects need to thoroughly understand signal and power integrity issues in order to successfully design packages and boards for high speed systems Now, for the first time, there's a complete guide to power integrity modeling: everything you need to know, from the basics through the state of the artUsing realistic case studies and downloadable software examples, two leading experts demonstrate today's best techniques for designing and modeling interconnects to efficiently distribute power and minimize noiseThe authors carefully introduce the core concepts of power distribution design, systematically present and compare leading techniques for modeling noise, and link these techniques to specific applications Their many examples range from the simplest (using analytical equations to compute power supply noise) through complex system-level applicationsThe authors Introduce power delivery network components, analysis, high-frequency measurement, and modeling requirements Thoroughly explain modeling of power/ground planes, including plane behavior, lumped modeling, distributed circuit-based approaches, and much more Offer in-depth coverage of simultaneous switching noise, including modeling for return currents using time- and frequency-domain analysis Introduce several leading time-domain simulation methods, such as macromodeling, and discuss their advantages and disadvantages Present the application of the modeling methods on several advanced case studies that include high-speed servers, high-speed differential signaling, chip package analysis, materials characterization, embedded decoupling capacitors, and electromagnetic bandgap structures This book's system-level focus and practical examples will make it indispensable for every student and professional concerned with power integrity, including electrical engineers, system designers, signal integrity engineers, and materials scientists It will also be valuable to developers building software that helps to analyze high-speed systems
271 citations
TL;DR: In this article, the authors provide an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.
Abstract: The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.
259 citations
"Overview of Power Integrity Solutio..." refers background in this paper
...The SI in terms of jitter and the eye opening of high-speed signals will be degraded by the fluctuated (or the noisy) dc power level [1], [2]....
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