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Proceedings ArticleDOI

Panel: Reconfigurable SoC- What will it look like

B. Lewis, Ivo Bolsens1, Rudy Lauwereins, C. Wheddon, B. Gupta2, Y. Tanurhan3 
04 Mar 2002-pp 660-662
TL;DR: A panel of key industryexecutives each coming from a different area of themarket with unique views will debate these highlycontroversial topics.
Abstract: The argument against ASIC SoCs is that they have always taken too long and cost too much to design. As new process technologies come on line, the issue of inflexible, unyielding designs fixed in silicon becomes a serious concern. Without the flexibility of reconfigurable logic, will standard cell ASICs disappear and go the way of gate arrays? Will ASIC manufacturers lose their edge in providing intellectual value and become mere purveyors of square die area? The argument in favor of FPGAs is that they have always provided great design flexibility because they were configurable. The argument against FPGAs is that compared to ASICs they have always been larger, slower and more expensive. Will FPGAs ever become efficient enough to replace ASICs in volume production applications? ASSPs can be designed with partial reconfigurability. Will they become the norm? Or, will new reconfigurable logic cores change the SoC game completely? The answers to these questions will clearly impact system designers throughout the world and shape the future of the electronics industry. A panel of key industry executives each coming from a different area of the market with unique views will debate these highly controversial topics.
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Journal ArticleDOI
TL;DR: It is shown that networks-on-chip (NoC) are an ideal communication layer for dynamically reconfigurable SoCs, and how the OS provides run-time support for dynamic task relocation is explained.

64 citations

01 Jan 2008
TL;DR: This thesis details the key components of such an MPSoC run-time manager and provides a proof-of-concept implementation, and introduces a novel task assignment algorithm for handling soft IP cores denoted as hierarchical con??guration.
Abstract: In recent years, we are witnessing the dawning of the Multi-Processor Systemon- Chip (MPSoC) era. In essence, this era is triggered by the need to handle more complex applications, while reducing overall cost of embedded (handheld) devices. This cost will mainly be determined by the cost of the hardware platform and the cost of designing applications for that platform. The cost of a hardware platform will partly depend on its production volume. In turn, this means that ??exible, (easily) programmable multi-purpose platforms will exhibit a lower cost. A multi-purpose platform not only requires ??exibility, but should also combine a high performance with a low power consumption. To this end, MPSoC devices integrate computer architectural properties of various computing domains. Just like large-scale parallel and distributed systems, they contain multiple heterogeneous processing elements interconnected by a scalable, network-like structure. This helps in achieving scalable high performance. As in most mobile or portable embedded systems, there is a need for low-power operation and real-time behavior. The cost of designing applications is equally important. Indeed, the actual value of future MPSoC devices is not contained within the embedded multiprocessor IC, but in their capability to provide the user of the device with an amount of services or experiences. So from an application viewpoint, MPSoCs are designed to ef??ciently process multimedia content in applications like video players, video conferencing, 3D gaming, augmented reality, etc. Such applications typically require a lot of processing power and a signi??cant amount of memory. To keep up with ever evolving user needs and with new application standards appearing at a fast pace, MPSoC platforms need to be be easily programmable. Application scalability, i.e. the ability to use just enough platform resources according to the user requirements and with respect to the device capabilities is also an important factor. Hence scalability, ??exibility, real-time behavior, a high performance, a low power consumption and, ??nally, programmability are key components in realizing the success of MPSoC platforms. The run-time manager is logically located between the application layer en the platform layer. It has a crucial role in realizing these MPSoC requirements. As it abstracts the platform hardware, it improves platform programmability. By deciding on resource assignment at run-time and based on the performance requirements of the user, the needs of the application and the capabilities of the platform, it contributes to ??exibility, scalability and to low power operation. As it has an arbiter function between different applications, it enables real-time behavior. This thesis details the key components of such an MPSoC run-time manager and provides a proof-of-concept implementation. These key components include application quality management algorithms linked to MPSoC resource management mechanisms and policies, adapted to the provided MPSoC platform services. First, we describe the role, the responsibilities and the boundary conditions of an MPSoC run-time manager in a generic way. This includes a de??nition of the multiprocessor run-time management design space, a description of the run-time manager design trade-offs and a brief discussion on how these trade-offs affect the key MPSoC requirements. This design space de??nition and the trade-offs are illustrated based on ongoing research and on existing commercial and academic multiprocessor run-time management solutions. Consequently, we introduce a fast and ef??cient resource allocation heuristic that considers FPGA fabric properties such as fragmentation. In addition, this thesis introduces a novel task assignment algorithm for handling soft IP cores denoted as hierarchical con??guration. Hierarchical con??guration managed by the run-time manager enables easier application design and increases the run-time spatial mapping freedom. In turn, this improves the performance of the resource assignment algorithm. Furthermore, we introduce run-time task migration components. We detail a new run-time task migration policy closely coupled to the run-time resource assignment algorithm. In addition to detailing a design-environment supported mechanism that enables moving tasks between an ISP and ??ne-grained recon??gurable hardware, we also propose two novel task migration mechanisms tailored to the Network-on-Chip environment. Finally, we propose a novel mechanism for task migration initiation, based on reusing debug registers in modern embedded microprocessors. We propose a reactive on-chip communication management mechanism. We show that by exploiting an injection rate control mechanism it is possible to provide a communication management system capable of providing a soft (reactive) QoS in a NoC. We introduce a novel, platform independent run-time algorithm to perform quality management, i.e. to select an application quality operating point at run-time based on the user requirements and the available platform resources, as reported by the resource manager. This contribution also proposes a novel way to manage the interaction between the quality manager and the resource manager. In order to have a the realistic, reproducible and ??exible run-time manager testbench with respect to applications with multiple quality levels and implementation tradev offs, we have created an input data generation tool denoted Pareto Surfaces For Free (PSFF). The the PSFF tool is, to the best of our knowledge, the ??rst tool that generates multiple realistic application operating points either based on pro??ling information of a real-life application or based on a designer-controlled random generator. Finally, we provide a proof-of-concept demonstrator that combines these concepts and shows how these mechanisms and policies can operate for real-life situations. In addition, we show that the proposed solutions can be integrated into existing platform operating systems.

10 citations

Cites background from "Panel: Reconfigurable SoC- What wil..."

  • ...This template lives up to the prediction that future MPSoC platforms will consist of a mixture of tiles, containing heterogeneous computing resources and memory resources, interconnected by a flexible and configurable on-chip communications fabric [27, 123, 130]....


01 Jan 2009
TL;DR: A framework to realize the rapid estimation of hardware area-time trade-off measures that can facilitate in the FPGA porting of C-codes segments and an architecture template is proposed in order to assist in the estimation of the data-path and control-path of the hardware generated to accelerate the C-code segment.
Abstract: FPGAs (Field-Programmable Gate Arrays) have become an attractive solution to meet the technological and market uncertainties in embedded processing. The advent of reconfigurable systems that incorporates microprocessor and FPGA on the same platform necessitates efficient hardware-software partitioning strategies in emerging design flows. However, commercially available design flows do not enable designers to make design explorations for effective hardware-software partitioning. In this thesis, we propose a framework to realize the rapid estimation of hardware area-time trade-off measures that can facilitate in the FPGA porting of C-codes segments. The proposed framework relies on the Trimaran compiler infrastructure for its advanced scheduling schemes to expose the inherent parallelism in C-based algorithms. The original VLIW machine model employed in Trimaran was modified to incorporate heterogeneous functional units that are well suited for efficient FPGA implementation. In addition, we have proposed an architecture template in order to assist in the estimation of the data-path and control-path of the hardware generated to accelerate the C-code segment. The proposed data-path estimation technique relies on bit-width analysis and a hybrid approach for the estimation of the area-time measures. The hybrid approach employs pre-characterized parameters and analytical models for area-time estimation. Our experiments show that the bit-width optimization technique employed leads to area reduction of up to 3 times. We have also proposed two methods to improve the estimation of the delay measures by taking into account the post implementation interconnect delay between the hardware components by addressing the slack distribution of all the combinatorial paths and floor-planning considerations to predict the placement of the hardware components on the FPGA. The area-time estimation of the control unit based on one-hot encoding scheme examines both the next-state decoding logic and control signal decoding logic provides an average error of only about 10% when compared to commercial tools. ATTENTION: The Singapore Copyright Act applies to the use of this document. Nanyang Technological University Library

1 citations