Parallel Processing in a Restructurable Computer System
TL;DR: This paper describes the organization, programming, and hardware of a variable structure computer system presently under construction at UCLA.
Abstract: Pragmatic problem studies predict gains in computation speeds in a variety of computational tasks when executed on appropriate problem-oriented configurations of the variable structure computer. The economic feasibility of the system is based on utilization of essentially the same hardware in a variety of special purpose structures. This capability is achieved by programmed or physical restructuring of a part of the hardware. Existence of important classes of problems which the variable structure computer system promises to render practically computable, as well as use of the system for experiments in computer organization and for evaluation of new circuits and devices warrant construction of a variable structure computer. This paper describes the organization, programming, and hardware of a variable structure computer system presently under construction at UCLA.
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TL;DR: The hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling are explored, and the software that targets these machines is focused on.
Abstract: Due to its potential to greatly accelerate a wide variety of applications, reconfigurable computing has become a subject of a great deal of research. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. In this survey, we explore the hardware aspects of reconfigurable computing machines, from single chip architectures to multi-chip systems, including internal structures and external coupling. We also focus on the software that targets these machines, such as compilation tools that map high-level algorithms directly to the reconfigurable substrate. Finally, we consider the issues involved in run-time reconfigurable systems, which reuse the configurable hardware during program execution.
1,666 citations
Book•
02 Nov 2007
TL;DR: This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology.
Abstract: The main characteristic of Reconfigurable Computing is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor. Reconfigurable computing systems join microprocessors and programmable hardware in order to take advantage of the combined strengths of hardware and software and have been used in applications ranging from embedded systems to high performance computing. Many of the fundamental theories have been identified and used by the Hardware/Software Co-Design research field. Although the same background ideas are shared in both areas, they have different goals and use different approaches.This book is intended as an introduction to the entire range of issues important to reconfigurable computing, using FPGAs as the context, or "computing vehicles" to implement this powerful technology. It will take a reader with a background in the basics of digital design and software programming and provide them with the knowledge needed to be an effective designer or researcher in this rapidly evolving field.
· Treatment of FPGAs as computing vehicles rather than glue-logic or ASIC substitutes
· Views of FPGA programming beyond Verilog/VHDL
· Broad set of case studies demonstrating how to use FPGAs in novel and efficient ways
531 citations
01 May 2001
TL;DR: A survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years is presented in this article, with a focus on the application domain of digital signal processing.
Abstract: Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.
This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.
390 citations
TL;DR: In this paper, the authors give a graph-theoretic model for the description and analysis of parallel computations, in which computation steps correspond to nodes of a graph and dependency between computation steps is represented by branches with which queues of data are associated.
Abstract: This paper gives a graph-theoretic model for the description and analysis of parallel computations. Within the model, computation steps correspond to nodes of a graph, and dependency between computation steps is represented by branches with which queues of data are associated. First, it is shown that each such computation graphGrepresents a unique computation, determined independently of operation times. Next, methods of determining whether such a computation terminates and of finding the number of performances of each computation step are developed. The maximal strongly connected subgraphs of G and the loops within these subgraphs play aooutnal role in this analysis. For example, use is made of the result that either every computation step within a strongly connected snbgroph of G is performed an infinite number of times, or none is. Finally, necessary and sufficient conditions for the lengths of data queues to remain bounded are derived.
389 citations
TL;DR: A model for parallel computations is given as a directed graph in which nodes represent elementary operations, and branches, data channels, and an algorithm is given for the determination of the number of initiations of each node in the graph defining a parallel computation.
Abstract: A model for parallel computations is given as a directed graph in which nodes represent elementary operations, and branches, data channels. The problem considered is the determination of an admissible schedule for such a computation; i.e. for each node determine a sequence of times at which the node initiates its operation. These times must be such that each node, upon initiation, is assured of having the necessary data upon which to operate. Necessary and sufficient conditions that a schedule be admissible are given. The computation rate of a given admissible schedule is defined and is shown to have a limiting value 1/p where p is a parameter dependent upon the cycles in the graph. Thus, the computation cannot proceed at a rate exceeding 1/p. For g ≥ p, the class of all periodic admissible schedules with period g is characterized by the solution space of a certain system of linear inequalities. In particular, then, the maximum computation rate of 1/p is attainable under a periodic admissible schedule with period p. A class of all-integer admissible schedules is given. Finally, an algorithm is given for the determination of the number of initiations of each node in the graph defining a parallel computation. An example for a system of difference equations is given in detail.
240 citations
References
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03 May 1960
TL;DR: The past decade has seen the development of productive fast electronic digital computers, but a growing number of important problems have been recorded which are not practicably computable by existing systems.
Abstract: The past decade has seen the development of productive fast electronic digital computers. Significant problems have been solved and significant numerical experiments have been executed. Moreover, as expected, a growing number of important problems have been recorded which are not practicably computable by existing systems. These latter problems have provided the incentive for the present development of several large scale digital computers with the goal of one or two orders of magnitude increase in overall computational speed.
271 citations
[...]
TL;DR: The SOLOMON (Simultaneous Operation Linked Ordinal Modular Network), a parallel network computer, is a new system involving the interconnections and programming, under the supervision of a central control unit, of many identical processing elements in an arrangement that can simulate directly the problem being solved.
Abstract: The SOLOMON (Simultaneous Operation Linked Ordinal Modular Network), a parallel network computer, is a new system involving the interconnections and programming, under the supervision of a central control unit, of many identical processing elements (as few or as many as a given problem requires), in an arrangement that can simulate directly the problem being solved.
161 citations
TL;DR: Two generalizations of Horner's rule, sometimes referred to as the nesting rule, which allow for parallel computation are presented here.
Abstract: Polynomials are generally evaluated by use of Horner's rule, sometimes referred to as the nesting rule. This rule is sequential and affords no opportunity for parallecl omputation, i.e., completion of several of the arithmetic operations simultaneously. Two generalizations of Horner's rule which allow for parallel computation are presented here.
Schedules and, in some cases, machine codes for evaluating a polynomial on a computer with several parallel arithmetic units are developed. Some advantages of the generalized rules in sequential computations on a computer with a single arithmetic unit are presented.
49 citations
TL;DR: The Jaeobi method of diagonalization ~md an available program utilizing an improved technique for its execution on existing computers are described and the predicted in~ creases in speed due to the organization and parallelism and then with the superimposed effect of higher speed circuitry are evaluated.
Abstract: Abslract. The design of a special purpose computer to operate in parallel with a general purpose computer to accelerate the diagonalization of real symmetric matrices is described. The entire system operates in a configuration described as the \"Fixed-Plus-Variable\" Structure Computer [1] such that the same elements used for the special computer may be reorganized for other problem applications. As a vehicle for this study it is assumed that problem properties dictated the choice of Jacobi's method. The Jaeobi method of diagonalization ~md an available program utilizing an improved technique for its execution on existing computers are described. The bases of decisions leading to design of the special purpose computer are explained. The nature of the supervisory control, which coordinates the activities of the general and speeiM purpose computers is detailed. The predicted in~ creases in speed due to the organization and parallelism and then with the superimposed effect of higher speed circuitry are evaluated.
24 citations
TL;DR: The properties of the supervisory control which integrate the operation of the ``fixed structure'' general purpose computer and the ``variable structure'' special purpose configurations are specified and the over-all computational gains evaluated.
Abstract: Sequential table look-up algorithms are proposed for the evaluation of ln x and exp x. Tables of pre-computed constants are utilized in transforming the argument into a range where the function may be approximated by a simpler polynomial. In the case of ln x, x is transformed so that it falls into a close neighborhood of 1; in the case of exp x, x is transformed to a close neighborhood of 0. These algorithms are particularly effective when mechanized so as to carry out the predetermined sequence of operations without waste manipulation. Such special purpose organization is reasonable within the variable structure part of UCLA's proposed Fixed-Plus-Variable structure computer, as the same equipment may be reorganized for use in other special purpose configurations at other times. In this paper the sequential table look-up algorithms and their speed advantages over existing subroutine approximation procedures are described. The design of special purpose configurations which leads to another factor of speed increase as compared to a stored program implementation of the algorithms is presented. The properties of the supervisory control which integrate the operation of the ``fixed structure'' general purpose computer and the ``variable structure'' special purpose configurations are specified and the over-all computational gains evaluated. An order-of-magnitude increase in speed compared to existing subroutines is predicted in both cases.
16 citations