Parasitic effects depending on shape of spacer region on FinFETs
27 Apr 2007-Vol. 6, Iss: 4, pp 83-87
TL;DR: Parasitic resistance and capacitance relating to spacer region of FinFETs were investigated by changing shape of the spacer regions in this paper, where the trade-off relationship between these two parasitic elements was demonstrated on the expansion of the fin width in the Spacer region.
Abstract: Parasitic resistance and capacitance relating to spacer region of FinFETs were investigated by changing shape of the spacer region. The trade-off relationship between these two parasitic elements was demonstrated on the expansion of the fin width in the spacer region. The gate delay characteristic of the FinFETs was optimized by gradual expansion with triangular shape. It was indicated that not only parasitic resistance but also parasitic capacitance on the spacer region was significant for transistor performance.
Citations
More filters
[...]
TL;DR: A novel integrated process for well controlled side-wall spacer formation was developed for fabrication based on the systematical investigation of the effects of the various etch conditions on etching profile and their impacts on the sidewall transistor gate structure.
Abstract: As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly critical manufacturing process. In recent CMOS technologies, side-wall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present approach to overcome these fabrication limitations. The spacer patterning technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical integrated lithography and etching processes. Generally relates to semiconductor manufacturing, and more particularly to nanotechnology fabrication feasibility for CMOS wafer process on gate spacer technology manufacture feasibility. A modified side-wall spacer patterning method was implemented for using conventional lithography and etching processing technology. Based on the systematical investigation of the effects of the various etch conditions on etching profile and their impacts on the sidewall transistor gate structure, a novel integrated process for well controlled side-wall spacer formation was developed for fabrication.
3 citations
[...]
01 Dec 2009
TL;DR: In this paper, a novel manufacturing process integration of complementary metal oxide semiconductor (CMOS) transistor architecture, which is incorporated into a sub-micron logic technology on 300 mm wafers, is described.
Abstract: As the technology node advances to the next generation, one of the biggest challenges is to achieve minimum pitch while maintaining device performance. This paper describes the details of a novel manufacturing process integration of complementary metal oxide semiconductor (CMOS) transistor architecture, which is incorporated into a sub-micron logic technology on 300 mm wafers. As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly critical manufacturing process. Moreover, the material of the sidewall spacer itself plays an important role, and its impact on device performance has been intensively discussed. Fabrication process results show that the offset spacer configuration and width can effectively increase the on-state driving current and reduce the off-state leakage current off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate spacer extension structure. A novel semiconductor fabrication process on gate spacer technology and electrical performance of nano-meter gate structure was included.
3 citations
[...]
TL;DR: In this paper, the authors proposed modified feasible etching processes integration on the formation processing for complementary metal oxide semiconductor nanofabrication process of gate spacer technology and electrical characteristics.
Abstract: As wafer nanotechnology gate is scaling down, the fabrication technology of gate spacer for transistor becomes more critical in manufacturing processes. Because wafer fabrication technologies, sidewall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present study is to overcome the fabrication processes limitations and proposed modified feasible etching processes integration on the formation processing for complementary metal oxide semiconductor nanofabrication process of gate spacer technology and electrical characteristics.
Journal Article•
[...]
TL;DR: In this paper, the authors describe the details of a novel manufacturing process integration of CMOS (Complementary Metal-Oxide-Semiconductor) transistor architecture, which is incorporated into a sub-micron logic technology on 300mm wafers.
Abstract: This paper describes the details of a novel manufacturing process integration of CMOS (Complementary Metal-Oxide-Semiconductor) transistor architecture, which is incorporated into a sub-micron logic technology on 300mm wafers. As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly important especially for high performance. Experimental manufacturing process results show that the offset spacer and width can effectively increase the on-state driving current Ion and reduce the off-state leakage current off due to the high vertical fringing electric field effect arising from the side capacitor comprising of gate/offset spacer/drain extension structure. This fringing field and, in turn, the Ion/Ioff current ratio and sub-threshold swing can be strongly enhanced by increasing the dielectric constant of the offset space. The minimum-sized features are finished not by photolithography but by the CVD (chemical vapor deposition) film thickness and plasma etching processes. Therefore, the spacer technology yields critical dimension variations of minimum-sized features that are much smaller than achieved by optimal etching process. As a result, the lateral length of the spacer structure can be well controlled and the electrical performance of the later formed semiconductor device can be well controlled as well. Therefore, the reliability of the semiconductor device is increased.
Related Papers (5)
[...]
[...]
[...]