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Proceedings ArticleDOI

Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and verification

TL;DR: This paper takes a large RTL design of an ASIC into consideration, analyzes the size of each module in terms of number of CLBs, I/Os, flip-flops, latches and applies the algorithm to partition it automatically into minimum number of FPGAs.
Abstract: The ASIC designs are growing larger everyday It is very hard to simulate these designs because the simulation time has risen tremendously An alternate solution is to partition the large design into modules and perform incremental simulation Hardware Embedded Simulation (HES) is a technology that facilitates incremental design verification of large ASICs On the other hand, since the introduction of FPGAs, they have been playing an important role in ASIC design cycle But due to very large size of today's ASIC designs (millions of gates) compared to FPGAs, it is not possible to fit an entire ASIC design into a single FPGA device This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs This paper takes a large RTL design of an ASIC into consideration, analyzes the size of each module in terms of number of CLBs, I/Os, flip-flops, latches and applies the algorithm to partition it automatically into minimum number of FPGAs

Summary (3 min read)

Emulation Dilemma

  • Weeks and days of simulation time are reduced to hours and minutes.
  • The emulation methodology uses commercially available Field Programmable Gate Arrays or custom processors to duplicate ASIC design.
  • Emulation is the only verification approach that can attain the speed required for verification of an ASIC design in the real operating environment.
  • Testing in the real environment (in circuit) rather than a simulated environment significantly increases the probability that the device will perform as required.

Emulation Methodologies

  • The emulation market has evolved into two methodologies.
  • This facilitates a better flow for incremental changes or reusable logic.
  • This along with the high level of expertise and support required for success has limited its use to only large projects with significant funding and no other alternatives.
  • There is typically a minimum threshold speed that the system can be reduced to.
  • Since Open System Emulation typically runs faster than Black Box Emulation, the slow down problem is reduced and the speed is rarely below the threshold requirement.

HES -PCI board

  • The HES (Hardware Embedded Simulation) environment consists of software simulator and HES boards and is used for speedy design development and verification.
  • If the authors use HES for ASIC designs, they need to convert RTL design into an FPGA code, using for example the Synplicity's Ceritify program.
  • HES can be used as functional simulation accelerator, providing typically 50 to 1000 times speed improvement over the best RTL simulators.
  • The authors do not have to know how to place design modules in HES because the HES Wizard will guide us through each step of the way.
  • If the emulation prototype speed goes below the minimum threshold due to multiplexing, it is impossible to emulate in the external environment causing the emulation project to fail.

Synthesizing the ASIC design

  • Since the ASIC design has to be partitioned and put into multiple FPGAs, it is necessary to extract the information about overall size of the design.
  • The size of the given design can be specified in terms of following parameters for each module (if the design is done using Verilog as the hardware description language) or the entity (if the design is done using VHDL) : 1. Total number of I/Os (Input Output devices).
  • Application specific Integrated Circuits are designed by the user himself.
  • The implying enhancement of integration density causes lower system costs, lower power consumption, higher speed, lower weight/ volume and lower risks for failures.
  • Because of these advantages, the share of ASICs is constantly rising in the world sales of integrated circuits.

Top Down design

  • Top down design is referred to as recursive partitioning of a system into sub-components until all the sub-components become manageable design parts.
  • Hardware components corresponding to the terminals of the tree are recursively wired to form the hierarchical wiring of the complete system.
  • The authors can also use the text editor in the analysis step (described next) for easy debugging of design source files.
  • Optimize logic for speed and area as directed by their design constraints, generating an FPGA netlist file that is ready for place and route.
  • Express allows us to divide a design between HDL and schematic input in any proportion and create virtually any design hierarchy.

FPGA Express Functions

  • Express creates optimized FPGA netlists from VHDL code, Verilog HDL code, and existing, unoptimized netlists in the following design flow: 1. Analyzes VHDL and Verilog HDL source files for correct syntax using the Synopsys industry-standard HDL language policy.
  • After the authors add the design sources, FPGA Express analyzes HDL files.
  • Express elaborates the logic for their design, using architecture-specific algorithms.
  • With the graphical user interface (GUI), the authors can enter constraints for their design in editable tables.
  • When it has completed optimization, FPGA Express generates a netlist ready for place-and-route.

DPM interface to FPGA Express:

  • The DPM package implements a set of API's for DPM parmers to access the synthesis and optimization capability of FPGA Express.
  • The major functionalities exported through this API are project mangement, constraint management, and error, warning and message management.

PARTITIONING ALGORITHM

  • The given ASIC design is described using VHDL or Verilog as the Hardware Description Language.
  • Set up the design and analyze the source files.
  • Once the design is synthesized and netlist is formed, all the information about the connections between different blocks can be achieved , based on which partitioning decision can be taken.
  • Now the next top level module is taken into consideration and steps 4-9 are repeated till all the top level modules in the entire ASIC design are covered.
  • Finally based on these results, the individual FPGA devices need to be synthesized and the final top level netlist needs to be generated.

Execution of the software code

  • Following are the steps needed for the execution of the software code written in C language.
  • Basically the code is capable of synthesizing and partitioning the given HDL ASIC Design into multiple FPGA devices.
  • Design stands for the name of the design Project stands for the name of the project.
  • The next step is to partition the modules using partition software.

Data tvpes

  • In Verilog there are pre-defined gate level primitives: and, or, xor, nand, nor, xnor.
  • These gates have multiple inputs and only one output.
  • KeyAvord identifiers are used to reference gate primitives along with the output and input signals.
  • Instance names are not required but they should be used , especially in case of more than one instantiations of the same module or primitive, also known as 2. Note.
  • The initial and always statement are executed in parallel.

Blocking assignments

  • Shall be executed before the execution of the statement that follow it in sequential block.
  • Shall not prevent the execution of statement that follow it in a parallel block.
  • Allows assignments scheduling without blocking the procedural flow, also known as Non-blocking assignments.
  • If a positive edge occurs on the clock (elk) then the counter value (q) will be incremented by one.
  • But when en goes from high to low then the procedural statement will be ended and y will be again driven by the continues assignment, A delay control begins with the # value character followed by the dealy value.

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UNLV Retrospective Theses & Dissertations
1-1-2000
Partitioning of large HDL ASIC designs into multiple FPGA devices Partitioning of large HDL ASIC designs into multiple FPGA devices
for prototyping and veri=cation for prototyping and veri=cation
Nilesh V Dhavlikar
University of Nevada, Las Vegas
Follow this and additional works at: https://digitalscholarship.unlv.edu/rtds
Repository Citation Repository Citation
Dhavlikar, Nilesh V, "Partitioning of large HDL ASIC designs into multiple FPGA devices for prototyping and
veri=cation" (2000).
UNLV Retrospective Theses & Dissertations
. 1240.
http://dx.doi.org/10.25669/jrm5-17mc
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PARTITIONING OF LARGE HDL ASIC DESIGNS INTO MULTIPLE FPGA
DEVICES FOR PROTOTYPING AND VERIFICATION
by
Nilesh Dhavlikar
Bachelor of Science in Electrical Engineering
University of Pune, India
1998
A thesis submitted in partial fulfillment
of the requirements for the
Masters of Science Degree in Electrical Engineering
Department of Electrical and Computer Engineering
Howard R. Hughes College of Engineering
Graduate College
University o f Nevada, Las Vegas
May 2001
Reproduced with permission of the copyright owner. Further reproduction prohibited without permission.

UMI Number: 1405097
Copyright 2001 by
Dhavlikar, Nilesh V.
All rights reserved.
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Citations
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Dissertation
01 Jan 2012

2 citations


Cites methods from "Partitioning of large HDL ASIC desi..."

  • ...With its high flexibility and short time-to-market, as indicated by Selvaraj, Sapiecha and Dhavlikar [44], this FPGA emulation has emerged as a major ASIC verification technology....

    [...]

Proceedings ArticleDOI
01 Jan 2005
TL;DR: A systematic approach for mixed abstraction execution in the SoftSONIC virtual hardware platform, which gives the possibility of gradual refinement and parallel development and verification of system components and can reduce the overall design time.
Abstract: This paper presents a systematic approach for mixed abstraction execution in the SoftSONIC virtual hardware platform. In mixed abstraction execution different levels of abstraction, for example clockless coarse granularity transaction level modelling (TLM) and clocked register transfer level (RTL) models can be co-simulated. When combining 10 Hz to 1 kHz-range RTL model of component under development with 100 kHz to 10 MHz-range TLM model of rest of the system, the full system simulates close to the speed of one RTL component alone. By verifying the components in full system simulation, error-prone and tedious per-component testbench generation can be avoided. Mixed abstraction execution also gives the possibility of gradual refinement and parallel development and verification of system components. These aspects can reduce the overall design time, as we show in this paper with the development of a real-time JPEG 2000 hardware encoder

1 citations


Cites background from "Partitioning of large HDL ASIC desi..."

  • ...It is a well know fact that RTL simulation is not fast enough to satisfy the requirements of complex digital design verification [3]–[5]....

    [...]

Proceedings ArticleDOI
07 Sep 2009
TL;DR: A new approach for multiple FPGA platform scheme suitable for today’s rapid growth of SoC ASIC designs is proposed and targets the modular verification approach for pre-silicon software verification instead of using the full scale system verification process.
Abstract: This paper addresses problems associated with verification and FPGA prototyping platform preparation for the pre-silicon software development. Increasing the size of modern SoC makes traditional approach of mapping entire design into one FPGA unsuitable. Consequently, other more appropriate scheme must be found in order to achieve optimal results. One solution for the problem could be platforms with 16 or more modern FPGAs. However, such platform verification cost would be significantly increased and most of the SoC designs would face serious issues during platform preparation if design concept is not adjusted to the specific verification process. In this paper we propose a new approach for multiple FPGA platform scheme suitable for today’s rapid growth of SoC ASIC designs. The proposed approach targets the modular verification approach for pre-silicon software verification instead of using the full scale system verification process.

Cites background from "Partitioning of large HDL ASIC desi..."

  • ...A modern SoC today can contain one or more Central processor units (CPU), memory interfaces (SDRAM, DDR2,…), audio and video processing units (Encoders, decoders,…), peripheral blocks (USB, Flash, SD, …) and interconnecting interfaces for configuration SCI (SoC shell interface) and for data…...

    [...]

References
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Book
01 Jan 1999

39 citations