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Book ChapterDOI

Performance Analysis of Five-Level-Cascaded H-Bridge Inverter

01 Jan 2021-pp 377-385
TL;DR: In this article, the performance analysis of conventional PWM inverters and the cascaded H-bridge multilevel PWM transformers is performed for MATLAB Simulink, with the help unipolar and bipolar switching schemes.
Abstract: Multilevel inverter structures have the several points of interest of running at high DC bus voltages for higher strength applications that is executed the utilization of an arrangement association of exchanging devices. Alternatively, reduction in the harmonics of the output voltage is accomplished via switching between distinctive voltage stages. The two important typical topologies of multilevel inverters are clamped diode inverter and the cascaded H-bridge inverter. In this article, we will talk about the multilevel-cascaded inverter. The multilevel-cascaded inverter uses single-phase complete bridge inverter sequence strings to create multilevel phase legs. A particular benefit of this topology is that every bridge has modular modulation, power, and security requirements. Also, topologies of multilevel inverters can produce a better quality of performance when operating at a lower frequency of switching. In this paper, the traditional PWM inverter is modeled for MATLAB Simulink. With the help unipolar and bipolar switching schemes, the performance analysis of conventional PWM inverters and the cascaded H-bridge multilevel PWM inverters is executed and the consequences are.
Citations
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01 Sep 2010

2,148 citations

References
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01 Sep 2010

2,148 citations

Journal ArticleDOI
TL;DR: The proposed method uses a simple mapping to achieve the SVPWM for a multilevel inverter based on standard two-level SVP WM, and the computation of on-times for an n-level inverter becomes easier.
Abstract: Multilevel inverters are increasingly being used in high-power medium voltage applications due to their superior performance compared to two-level inverters. Among various modulation techniques for a multilevel inverter, the space vector pulsewidth modulation (SVPWM) is widely used. However, the implementation of the SVPWM for a multilevel inverter is complicated. The complexity is due to the difficulty in determining the location of the reference vector, the calculation of on-times, and the determination and selection of switching states. This paper proposes a general SVPWM algorithm for multilevel inverters based on standard two-level SVPWM. Since the proposed multilevel SVPWM method uses two-level modulation to calculate the on-times, the computation of on-times for an n-level inverter becomes easier. The proposed method uses a simple mapping to achieve the SVPWM for a multilevel inverter. A general n-level implementation is explained, and experimental results are given for three-level and five-level inverters

422 citations

Journal ArticleDOI
TL;DR: In this paper, an active harmonic elimination method was proposed to eliminate any number of specific higher order harmonics of multilevel converters with equal or unequal dc voltages, and the simulation results showed that the method can effectively eliminate the specific harmonics, and a low total harmonic distortion (THD) near sine wave was produced.
Abstract: This paper presents an active harmonic elimination method to eliminate any number of specific higher order harmonics of multilevel converters with equal or unequal dc voltages. First, resultant theory is applied to transcendental equations characterizing the harmonic content to eliminate low order harmonics and to determine switching angles for the fundamental frequency switching scheme and a unipolar switching scheme. Next, the residual higher order harmonics are computed and subtracted from the original voltage waveform to eliminate them. The simulation results show that the method can effectively eliminate the specific harmonics, and a low total harmonic distortion (THD) near sine wave is produced. An experimental 11-level H-bridge multilevel converter with a field programmable gate array controller is employed to implement the method. The experimental results show that the method does effectively eliminate any number of specific harmonics, and the output voltage waveform has low THD.

322 citations

Journal ArticleDOI
TL;DR: The proposed single-phase cascaded MLI topology is designed with the aim of reducing the number of switches and theNumber of dc voltage sources with modularity while having a higher number of levels at the output.
Abstract: Multilevel inverters (MLIs) are a great development for industrial and renewable energy applications due to their dominance over conventional two-level inverter with respect to size, rating of switches, filter requirement, and efficiency. A new single-phase cascaded MLI topology is suggested in this paper. The proposed MLI topology is designed with the aim of reducing the number of switches and the number of dc voltage sources with modularity while having a higher number of levels at the output. For the determination of the magnitude of dc voltage sources and a number of levels in the cascade connection, three different algorithms are proposed. The optimization of the proposed topology is aimed at achieving a higher number of levels while minimizing other parameters. A detailed comparison is made with other comparable MLI topologies to prove the superiority of the proposed structure. A selective harmonic elimination pulse width modulation technique is used to produce the pulses for the switches to achieve high-quality voltage at the output. Finally, the experimental results are provided for the basic unit with 11 levels and for cascading of two such units to achieve 71 levels at the output.

189 citations

Journal ArticleDOI
TL;DR: A novel three-dimensional (3-D) space-vector algorithm for four-leg multilevel converters is presented that can be applied to active power filters or neutral-current compensator applications for mitigating harmonics and zero-sequence components using abc coordinates.
Abstract: In this paper, a novel three-dimensional (3-D) space-vector algorithm for four-leg multilevel converters is presented. It can be applied to active power filters or neutral-current compensator applications for mitigating harmonics and zero-sequence components using abc coordinates (referred from now on this paper as natural coordinates). This technique greatly simplifies the selection of the 3-D region where a given voltage vector is supposed to be found. Compared to a three-level modulation algorithm for three-leg multilevel converters, this algorithm does not increase its complexity and the calculations of the active vectors with the corresponding switching time that generate the reference voltage vector. In addition, the low-computational cost of the proposed algorithm is always the same and it is independent of the number of levels of the converter.

131 citations