Proceedings ArticleDOI
Performance Analysis of Parallel Prefix Adder for Datapath Vlsi Design
K. C. Shilpa,M. Shwetha,B.C. Geetha,D. M. Lohitha,Navya,N.V. Pramod +5 more
- pp 1552-1555
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TLDR
This paper proposed four type of Parallel prefix adder (PPA) like Sklansky adder, Kogge-StoneAdder, Brent-Kung adder and Ladner-Fischer adder which are suited for binary addition with wide word.Abstract:
All modern processor, including microprocessor, digital signal processor contain Arithmetic Logic Unit (ALU). The computing efficiency of these modern processor mainly depended on efficiency of ALU. An adder is the basic building block for an ALU which performs arithmetic as well as logic operations. The existing adders like half adder, full adder, ripple carry adder, carry skip adder and carry lookahead adders cannot meet the expected optimization goals, so in this paper proposed four type of Parallel prefix adder (PPA) like Sklansky adder, Kogge-Stone adder, Brent-Kung adder and Ladner-Fischer adder. Parallel prefix adder [PPA] are kind of adder that uses prefix operation in order to do efficient addition. These adders are suited for binary addition with wide word. The Parallel prefix adders are derived from the carry look ahead adder. The performance analysis of PPA considered on area, delay and power consumption and simulation are carried out for 8 bit input data width.read more
Citations
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Journal ArticleDOI
Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications
TL;DR: In this paper, an efficient hardware architecture of Optimized Haar Wavelet Transform (DWT) is proposed which is modeled using Optimized Kogge-Stone Adder/Subtractor, Optimized Controller, Buffer, Shifter and D_FF blocks.
Proceedings ArticleDOI
Implementation of modified Dual-CLCG Method for Pseudorandom bit Generation
B Sunandha,P Sathish Kumar +1 more
TL;DR: The “Modified dual-CLCG” method, said to be secure pseudorandom bit sequence(PRBG) among the various available LFSR, LCG, Dual CLCG that generates a Pseudo-Congruential bit sequence at a periodic interval that depends on the inequality equations.
Journal ArticleDOI
Fast Large Integer Modular Addition in GF(p) Using Novel Attribute-Based Representation
Bader Alhazmi,Fayez Gebali +1 more
TL;DR: A novel and efficient attribute-based large integer representation scheme suitable for large integers commonly used in cryptography such as the five NIST primes and the Pierpont primes used in supersingular isogeny Diffie–Hellman (SIDH) for post-quantum cryptography is proposed.
Proceedings ArticleDOI
Comparative analysis of 16-tap FIR filter design using different adders
TL;DR: Experimental results show that efficiency in power-delay product can be obtained by using Carry Increment Adder for FIR filter design than that of various other multi-bit adder structures.
Proceedings ArticleDOI
A Proposed Design of Conventional 4-Bit Carry Look-Ahead Adder Improving Performance
TL;DR: This paper has proposed an advanced version of CLA adder where hybrid logic based XOR gate and GDI AND gates have been used as input to reduce the transistor count as well as to improve performance.
References
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Book
CMOS VLSI Design : A Circuits and Systems Perspective
Neil Weste,David Money Harris +1 more
TL;DR: The authors draw upon extensive industry and classroom experience to introduce todays most advanced and effective chip design practices, and present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples.
Journal ArticleDOI
A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations
Peter M. Kogge,Harold S. Stone +1 more
TL;DR: This paper uses a technique called recursive doubling in an algorithm for solving a large class of recurrence problems on parallel computers such as the Iliac IV.
Journal ArticleDOI
A Regular Layout for Parallel Adders
TL;DR: It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Journal ArticleDOI
A reduced-area scheme for carry-select adders
TL;DR: The author introduces a scheme to generate carry bits with block-carry-in 1 from the carries of a block withBlock- Carry-in 0 to derive a more area-efficient implementation for both the carry-select and parallel-prefix adders.
Journal ArticleDOI
High-speed parallel-prefix VLSI Ling adders
TL;DR: Experimental results reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the fastest parallel-prefix architectures presented for the traditional definition of carry equations.