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Proceedings ArticleDOI

Performance analysis of radix-2/3/5 decompositions in fixed point DIT FFT algorithms

TL;DR: This work proposes a variable-length FFT processor that can be reconfigured that achieves better specifications for area use and delay and makes a clear comparison between different radices and the efficiency associated with each of them.
Abstract: In this article, we focus on the extensively utilized algorithm for Fast Fourier Transform (FFT) radix-2 DecimationInTime (DIT). It proposes a variable-length FFT processor that can be reconfigured. The processor designed for different FFT / IFFT stages can perform 8, 16 and 32 point FFT / IFFT with different word length scaling modes. Furthermore, in many applications, the processor is suitable for various FFT / IFFT length requirements. Single-path delay feedback (SDF) pipeline architecture is incorporated in order to achieve higher throughput. Cadence NC Launch, RTL Compiler, Simvision Simulator and Altera DE2 FPGA EP2C35F672C6 board are used to test the design in TSMC 45 nm technology. We often worked with 2/3/5 radices and thus make a clear comparison between different radices and the efficiency associated with each of them. This work achieves better specifications for area use and delay. Meanwhile, the occupied resources are approximately same. Moreover, the performance of different FFT length is analyzed.
Citations
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Proceedings ArticleDOI
11 Dec 2020
TL;DR: In this article, the authors proposed two 6mpoint split radix fast Fourier transform (SRFFT) algorithms, where the complex numbers are represented in a special basis (1, μ) and μ is the complex cube root of unity.
Abstract: In this paper, we focus on the extensively utilized algorithm for split radix FFT. It proposes two the 6mpoint split radix fast Fourier transform (SRFFT), where the complex numbers are represented in a special basis (1, μ) and μ is the complex cube root of unity. Two SRFFTs, termed radix-2/6 and radix-3/6, are proposed and both algorithms are based on radix 2 and radix 3 FFT. Furthermore, we utilize them to design appropriate algorithm structure for length 6m• In addition, fast multiplication in (1, μ) is also proposed. Compared with prior results, the proposed SRFFT requires fewer real multiplications. To our knowledge, this is the first SRFFTs over the basis (1, μ) and this work achieves better specifications for area use and delay. Meanwhile, the occupied resources are approximately same. Moreover, the performance of different FFT length is analyzed.

1 citations

Proceedings ArticleDOI
13 Mar 2023
TL;DR: In this paper , a 64-point DFT method based on radix-4 FFT and multi-stage strategy is presented, based on the results of simulations with Xilinx ISE, it can be concluded that the algorithm developed is faster than conventional approaches, with an 18.963 ns delay and 12.68 mW of power consumption.
Abstract: : For front-end wireless applications in small battery-powered devices, discrete Fourier transform (DFT) is a critical processing method for discrete time signals. Advanced radix structures are created to reduce the impact of transistor malfunction. To develop DFT, with radix sizes 4, 8, etc., is a complex and tricky issue for algorithm designers. The main reason for this is that the butterfly algorithm’s lower-radix-level equations were manually estimated. This requires the selection of a new design process. As a result of fewer calculations and smaller memory requirements for computationally intensive scientific applications, this research focuses on the radix-4 fast Fourier-transform (FFT) technique. A new 64-point DFT method based on radix-4 FFT and multi-stage strategy to solve DFT-related issues is presented in this paper. Based on the results of simulations with Xilinx ISE, it can be concluded that the algorithm developed is faster than conventional approaches, with an 18.963 ns delay and 12.68 mW of power consumption. It was found that the computed picture compression drop ratios of 0.10, 0.31, 0.61 and 0.83 had a direct relationship to the varied tolerances tested, 0.0007625, 0.003246, 0.013075 and 0.03924. Fast reconstruction techniques, wireless medical devices and other applications benefit from this FFT’s low power consumption, small storage requirements, and high processing speed.
References
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Journal ArticleDOI
TL;DR: Good generalized these methods and gave elegant algorithms for which one class of applications is the calculation of Fourier series, applicable to certain problems in which one must multiply an N-vector by an N X N matrix which can be factored into m sparse matrices.
Abstract: An efficient method for the calculation of the interactions of a 2' factorial ex- periment was introduced by Yates and is widely known by his name. The generaliza- tion to 3' was given by Box et al. (1). Good (2) generalized these methods and gave elegant algorithms for which one class of applications is the calculation of Fourier series. In their full generality, Good's methods are applicable to certain problems in which one must multiply an N-vector by an N X N matrix which can be factored into m sparse matrices, where m is proportional to log N. This results inma procedure requiring a number of operations proportional to N log N rather than N2. These methods are applied here to the calculation of complex Fourier series. They are useful in situations where the number of data points is, or can be chosen to be, a highly composite number. The algorithm is here derived and presented in a rather different form. Attention is given to the choice of N. It is also shown how special advantage can be obtained in the use of a binary computer with N = 2' and how the entire calculation can be performed within the array of N data storage locations used for the given Fourier coefficients. Consider the problem of calculating the complex Fourier series N-1 (1) X(j) = EA(k)-Wjk, j = 0 1, * ,N- 1, k=0

11,795 citations


"Performance analysis of radix-2/3/5..." refers methods in this paper

  • ...Mathematically, twiddle factor WN can be represented as, N/2j N eW π−= (3) Cooley-Tukey [13] algorithm is used to decompose larger DFTs into several smaller DFTs....

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  • ...Mathematically, twiddle factor WN can be represented as, N / 2 j N e W π − = (3) Cooley-Tukey [13] algorithm is used to decompose larger DFTs into several smaller DFTs....

    [...]

Journal ArticleDOI
TL;DR: Given a vector of N elements, the perfect shuffle of this vector is a permutation of the elements that are identical to aperfect shuffle of a deck of cards.
Abstract: Given a vector of N elements, the perfect shuffle of this vector is a permutation of the elements that are identical to a perfect shuffle of a deck of cards. Elements of the first half of the vector are interlaced with elements of the second half in the perfect shuffle of the vector.

1,331 citations


Additional excerpts

  • ...Table 6 Comparison with existing works Parameter This Work [20] [21] [22] [23] [24]...

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Book
03 Oct 2008
TL;DR: In this paper, the authors present an up-to-date coverage of the recently published LTE Release 8 radio access standard, giving the reader insight into the ongoing and future process of LTE and LTE-Advanced standardisation.
Abstract: Reflecting the recent completion of LTEs specification, the new edition of this bestseller has been fully updated to provide a complete picture of the LTE system. The latest LTE standards are included on the radio interface architecture, the physical layer, access procedures, MBMS, together with three brand new chapters on LTE Transmission Procedures, Flexible Bandwidth in LTE and LTE evolution into IMT-Advanced. Key technologies presented include multi-carrier transmission, advanced single-carrier transmission, advanced receivers, OFDM, MIMO and adaptive antenna solutions, advanced radio resource management and protocols, and different radio network architectures. Their role and use in the context of mobile broadband access in general is explained. Both a high-level overview and more detailed step-by-step explanations of HSPA and LTE implementation are given. An overview of other related systems such as TD SCDMA, CDMA2000, and WiMAX is also provided.The new edition has up-to-date coverage of the recently published LTE Release 8 radio-access standard, giving the reader insight into the ongoing and future process of LTE and LTE-Advanced standardisation. Coverage on LTE in this edition includes (an extra 160 pages): Easy-to-access overview of the LTE protocol layers Complete description of LTE physical layer including reference signals, control signalling, multi-antenna transmission schemes Covers both FDD and TDD, their fundamental difference and their impact on the LTE design Detailed description of access procedures including cell search, random access, broadcast of system information Transmission procedures, including retransmission protocols, scheduling, uplink power control Evolution towards IMT-Advanced ("4G") This book is a must-have resource for engineers and other professionals in the telecommunications industry, working with cellular or wireless broadband technologies, giving an understanding of how to utilize the new technology in order to stay ahead of the competition.The authors of the book all work at Ericsson Research and are deeply involved in 3G development and standardisation since the early days of 3G research. They are leading experts in the field and are today still actively contributing to the standardisation of both HSPA and LTE within 3GPP.* Includes details of the standards and technologies (160 new pages): LTE radio interface architecture, LTE physical layer and LTE access procedures* Contains three brand new chapters on LTE: Transmission Procedures, Flexible Bandwidth and LTE Evolution and expanded details on the physical layer (total LTE content is 270 pages)* Examines the latest developments in the evolution of LTE into IMT-Advanced, the next stage of 3G Evolution* Gives clear explanations of the role of OFDM and MIMO technologies in HSPA and LTE* Outlines the System Architecture Evolution (SAE) supporting LTE and HSPA evolution

242 citations

Journal ArticleDOI
TL;DR: A new formulation of fast Fourier transformation kernels for radix 2, 3, 4, and 5 are presented, which have a perfect balance of multiplies and adds and give higher performance on machines that have a single multiply--add (mult--add) instruction.
Abstract: We present a new formulation of fast Fourier transformation (FFT) kernels for radix 2, 3, 4, and 5, which have a perfect balance of multiplies and adds. These kernels give higher performance on machines that have a single multiply--add (mult--add) instruction. We demonstrate the superiority of this new kernel on IBM and SGI workstations.

181 citations


"Performance analysis of radix-2/3/5..." refers background in this paper

  • ...Other radices, including radix 5, have been specified for computing, though not definitively aimed for hardware implementation [12]....

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Journal ArticleDOI
TL;DR: A new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy that can reduce hardware complexity and computation cycles compared with existing FFT processors is proposed.
Abstract: The paper proposes a new continuous-flow mixed-radix (CFMR) fast Fourier transform (FFT) processor that uses the MR (radix-4/2) algorithm and a novel in-place strategy. The existing in-place strategy supports only a fixed-radix FFT algorithm. In contrast, the proposed in-place strategy can support the MR algorithm, which allows CF FFT computations regardless of the length of FFT. The novel in-place strategy is made by interchanging storage locations of butterfly outputs. The CFMR FFT processor provides the MR algorithm, the in-place strategy, and the CF FFT computations at the same time. The CFMR FFT processor requires only two N-word memories due to the proposed in-place strategy. In addition, it uses one butterfly unit that can perform either one radix-4 butterfly or two radix-2 butterflies. The CFMR FFT processor using the 0.18 /spl mu/m SEC cell library consists of 37,000 gates excluding memories, requires only 640 clock cycles for a 512-point FFT and runs at 100 MHz. Therefore, the CFMR FFT processor can reduce hardware complexity and computation cycles compared with existing FFT processors.

128 citations