Performance-driven compaction for analog integrated circuits

Abstract: A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach.

Abstract: A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from high-level performance specifications by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching information on devices and interconnect as well as graph-based techniques to extract the necessary geometric information.

Abstract: An algorithm for the automatic generation of full-stacked layouts in CMOS analog circuits is described in this paper. The set of stacks obtained is optimum with respect to a cost function which accounts for critical parasitics and device area minimization. Device interleaving and common-centroid patterns are automatically introduced when possible, and all symmetry and matching constraints are enforced. The algorithm is based on operations performed on a graph representation of circuit connectivity, exploiting the equivalence between stack generation and path partitioning in the circuit graph. Path partitioning is carried out in two phases: in the first phase, all paths are generated by a dynamic programming procedure. In the second phase, the optimum partition is selected by solving a clique problem. Original heuristics have been introduced, which preserve the optimality of the solution, while effectively improving the computational efficiency of the algorithm. The algorithm has been implemented in the "C" programming language. Many test cases have been run, and the quality of results is comparable to that of hand-made circuits. Results also demonstrate the effectiveness of the heuristics employed, even for relatively complex circuits. >

Abstract: Layout for analog circuits has historically been a time consuming, manual, trial-and-error task. The problem is not so much the size (in terms of the number of active devices) of these designs, but rather the plethora of possible circuit and device interactions: from the chip substrate, from the devices and interconnects themselves, from the chip package. In this short survey we enumerate briefly the basic problems faced by those who need to do layout for analog and mixed-signal designs, and survey the evolution of the design tools and geometric/electrical optimization algorithms that have been directed at these problems.

Abstract: This paper describes a novel analog module generator environment for the automatic layout development of analog circuits. The C++ tool features a novel procedural layout description language that drastically eases the creation of analog modules. Due to the object oriented programming the designer can specify the modules in a hierarchical way using elementary geometrical primitives and conditional statements. The primitive objects are placed relatively and are abutted with the help of a special compactor. An optimization routine with backtracking capability facilitates the creation of high quality analog layouts. A layout example of a broad-band BiCMOS amplifier will demonstrate the usability of the tool.

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Abstract: The authors describe KOAN and ANAGRAM II, new tools for device-level analog placement and routing. Analog layout tools that merely apply known digital macrocell techniques fall short of achieving the density and performance of handcrafted analog cells. KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators. New placement algorithms implemented in KOAN handle complex layout symmetries, dynamic merging and abutment of individual devices, and flexible generation of wells and bulk constants. New routing algorithms implemented in ANAGRAM II handle arbitrary gridless design rules in addition to over-the-device, crosstalk-avoiding, mirror-symmetric, and self-symmetric wiring. Examples of CMOS and BiCMOS analog cell layouts produced by these tools are presented. >

Abstract: The authors describe KOAN and ANAGRAM II, new tools for device-level analog placement and routing. Analog layout tools that merely apply known digital macrocell techniques fall short of achieving the density and performance of handcrafted analog cells. KOAN and ANAGRAM II differ from previous approaches by using general algorithmic techniques to find critical device-level layout optimizations rather than relying on a large library of fixed-topology module generators. New placement algorithms implemented in KOAN handle complex layout symmetries, dynamic merging and abutment of individual devices, and flexible generation of wells and bulk constants. New routing algorithms implemented in ANAGRAM II handle arbitrary gridless design rules in addition to over-the-device, crosstalk-avoiding, mirror-symmetric, and self-symmetric wiring. Examples of CMOS and BiCMOS analog cell layouts produced by these tools are presented. >

Abstract: This paper describes a top-down, constraint-driven design methodology for analog integrated circuits. Some of the tools that support this methodology are described. These include behavioral simulation tools, tools for physical assembly, and module generators. Finally, examples of behavioral simulation with optimization and physical assembly are provided to better illustrate the methodology and its integration with the tool set.