Performance-driven compaction for analog integrated circuits
09 May 1993-
TL;DR: A novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality is described.
Abstract: The authors describe a novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. The approach consists of two stages: a fast constraint graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets. The algorithm has been implemented and found to display remarkable completeness and efficiency.
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TL;DR: A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented, guaranteeing that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment.
Abstract: A methodology for the automatic synthesis of full-custom IC layout with analog constraints is presented. The methodology guarantees that all performance constraints are met when feasible, or otherwise, infeasibility is detected as soon as possible, thus providing a robust and efficient design environment. In the proposed approach, performance specifications are translated into lower-level bounds on parasitics or geometric parameters, using sensitivity analysis. Bounds can be used by a set of specialized layout tools performing stack generation, placement, routing, and compaction. For each tool, a detailed description is provided of its functionality, of the way constraints are mapped and enforced, and of its impact on the design flow. Examples drawn from industrial applications are reported to illustrate the effectiveness of the approach.
162 citations
07 Nov 1993
TL;DR: A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits.
Abstract: A general methodology is presented for the generation of a complete set of constraints on interconnect parasitics, parasitic mismatch and on the physical topology of analog circuits. The parasitic and matching constraints are derived from high-level performance specifications by means of sensitivity analysis in time and frequency domain using quadratic optimization. Topological constraints are obtained by using sensitivity and matching information on devices and interconnect as well as graph-based techniques to extract the necessary geometric information.
53 citations
TL;DR: An algorithm for the automatic generation of full-stacked layouts in CMOS analog circuits is described, and the quality of results is comparable to that of hand-made circuits.
Abstract: An algorithm for the automatic generation of full-stacked layouts in CMOS analog circuits is described in this paper. The set of stacks obtained is optimum with respect to a cost function which accounts for critical parasitics and device area minimization. Device interleaving and common-centroid patterns are automatically introduced when possible, and all symmetry and matching constraints are enforced. The algorithm is based on operations performed on a graph representation of circuit connectivity, exploiting the equivalence between stack generation and path partitioning in the circuit graph. Path partitioning is carried out in two phases: in the first phase, all paths are generated by a dynamic programming procedure. In the second phase, the optimum partition is selected by solving a clique problem. Original heuristics have been introduced, which preserve the optimality of the solution, while effectively improving the computational efficiency of the algorithm. The algorithm has been implemented in the "C" programming language. Many test cases have been run, and the quality of results is comparable to that of hand-made circuits. Results also demonstrate the effectiveness of the heuristics employed, even for relatively complex circuits. >
42 citations
Cites methods from "Performance-driven compaction for a..."
...The partitions obtained have been used as starting configurations by analog layout tools for automatic placement [ 101, routing [l 11 and compaction [ 29 ], with excellent results....
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01 May 2000
TL;DR: This short survey enumerates briefly the basic problems faced by those who need to do layout for analog and mixed-signal designs, and survey the evolution of the design tools and geometric/electrical optimization algorithms that have been directed at these problems.
Abstract: Layout for analog circuits has historically been a time consuming, manual, trial-and-error task. The problem is not so much the size (in terms of the number of active devices) of these designs, but rather the plethora of possible circuit and device interactions: from the chip substrate, from the devices and interconnects themselves, from the chip package. In this short survey we enumerate briefly the basic problems faced by those who need to do layout for analog and mixed-signal designs, and survey the evolution of the design tools and geometric/electrical optimization algorithms that have been directed at these problems.
38 citations
11 Mar 1996
TL;DR: A novel analog module generator environment for the automatic layout development of analog circuits and a novel procedural layout description language that drastically eases the creation of analog modules is described.
Abstract: This paper describes a novel analog module generator environment for the automatic layout development of analog circuits. The C++ tool features a novel procedural layout description language that drastically eases the creation of analog modules. Due to the object oriented programming the designer can specify the modules in a hierarchical way using elementary geometrical primitives and conditional statements. The primitive objects are placed relatively and are abutted with the help of a special compactor. An optimization routine with backtracking capability facilitates the creation of high quality analog layouts. A layout example of a broad-band BiCMOS amplifier will demonstrate the usability of the tool.
24 citations
Cites background from "Performance-driven compaction for a..."
...In contrast to general compaction approaches [17, 18], the compaction is done successively by involving only one new object in each step....
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References
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01 Nov 1992
TL;DR: An efficient approach to the symbolic compaction of analog integrated circuits is presented, which allows the use of the compactor for very complex analog circuits with multiple symmetrics and other performance constraints.
Abstract: An efficient approach to the symbolic compaction of analog integrated circuits is presented. A fast graph-based algorithm performs a preliminary compaction taking into account a set of basic spacing constraints. The obtained configuration provides the starting point for a linear program, which optimizes the layout introducing multiple device and wire symmetry constraints. The efficiency and robustness of this technique allow the use of the compactor for very complex analog circuits with multiple symmetrics and other performance constraints. >
22 citations
"Performance-driven compaction for a..." refers background or methods in this paper
...In [5] symmetries are enforced with a combination graph and LP algorithm which uses constraint graph longest path techniques to arrive at a good starting point for an LP solver....
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...The details of using the constraint graph and LP solver together to enforce symmetries are reported in [5]....
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...The work presented in [5] served as a basis for the results presented here, with the primary contributions of this paper being: 1) a new aggressive technique for controlling parasitics and 2) an original technique for global wire length minimization....
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...Under these conditions the optimum solution to the LP problem contains only integer coordinates [5]....
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01 Jul 1992
TL;DR: In this article, a hierarchical compactor capable of compacting and pitchmatching hierarchically defined layouts is described, which enables compaction time to be a function of the irregularity rather than the size of the layout.
Abstract: A new hierarchical compactor capable of compacting and pitchmatching hierarchically defined layouts is described. The hierarchical compactor can handle most input hierarchies, including multilevel hierarchies, over the cell routing and cell rotations and reflections. The compactor simultaneously compacts the contents of all the cells of the layout hierarchy maintaining the hierarchy of the input layout as well as the pitchmaking and abutment constraints between the cells. The hierarchical compactor automatically factors out the regularity in the layout and performs almost all of its operations on a minimum design. This novel and unique formulation of the hierarchical compaction problem enables compaction time to be a function of the irregularity rather than the size of the layout. >
17 citations
Additional excerpts
...This technique is particularly appropriate when hierarchical compaction is performed [4]....
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