Performance-driven global routing for cell based ICs
14 Oct 1991-pp 170-173
TL;DR: The issue of delay optimization during the global routing phase is addressed, formulated as the construction of a bounded-radius spanning tree for a given pointset in the plane, and a family of effective heuristics is presented.
Abstract: Advances in VLSI technology and the increased complexity of circuit designs cause performance to become an increasingly important constraint for layout. The issue of delay optimization during the global routing phase is addressed. This problem is formulated as the construction of a bounded-radius spanning tree for a given pointset in the plane, and a family of effective heuristics is presented. This approach has very good empirical performance with respect to total wirelength, and can be smoothly tuned between the competing requirements of minimum delay and minimum total netlength, as confirmed by extensive computational results which confirm this. Extensions can be made to the graph and Steiner versions of the problem, and a number of open problems are described. >
Citations
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TL;DR: A comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for high-performance V LSI circuit design under the deep submicron fabrication technologies.
324 citations
TL;DR: A simple algorithm to find a spanning tree that simultaneously approximates a shortest-path tree and a minimum spanning tree is given and obtains the best-possible tradeoff.
Abstract: We give a simple algorithm to find a spanning tree that simultaneously approximates a shortest-path tree and a minimum spanning tree. The algorithm provides a continuous tradeoff: given the two trees and aź>0, the algorithm returns a spanning tree in which the distance between any vertex and the root of the shortest-path tree is at most 1+ź2ź times the shortest-path distance, and yet the total weight of the tree is at most 1+ź2/ź times the weight of a minimum spanning tree. Our algorithm runs in linear time and obtains the best-possible tradeoff. It can be implemented on a CREW PRAM to run a logarithmic time using one processor per vertex.
210 citations
Cites background or methods from "Performance-driven global routing f..."
...Cong, Kahng, Robins, Sarrafzadeh and Wong [7, 8, 9], motivated by applications in VLSI-circuit design, improve the constants in the construction of [2] and consider variations bounding the radius of the tree instead of the diameter....
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...We would like to thank Andrew Kahng and Jeff Salowe for telling us about [7, 8, 9]....
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TL;DR: A provably good performance-driven global routing algorithm for both cell-based and building-block design based on a new bounded-radius minimum routing tree formulation, based on an analog of Prim's minimum spanning tree construction.
Abstract: The authors propose a provably good performance-driven global routing algorithm for both cell-based and building-block design. The approach is based on a new bounded-radius minimum routing tree formulation. The authors first present several heuristics with good performance, based on an analog of Prim's minimum spanning tree construction. Next, they give an algorithm which simultaneously minimizes both routing cost and the longest interconnection path, so that both are bounded by small constant factors away from optimal. They also show that geometry helps in routing: in the Manhattan plane, the total wire length for Steiner routing improves to 3/2*(1+(1/ epsilon )) times the optimal Steiner tree cost, while in the Euclidean plane, the total cost is further reduced to (2/ square root 3)*(1+(1/ epsilon )) times optimal. The method generalizes to the case where varying wire length bounds are prescribed for different source-sink paths. Extensive simulations confirm that this approach works well. >
204 citations
Book•
31 Dec 1994
TL;DR: The Domain of Discourse: Routing in VLSI Physical Design is illustrated with examples of Steiner Trees in Graphs, an early Matching-Based approach to Delay Minimization, and its application to Signal Delay Estimators.
Abstract: List of Figures. List of Tables. 1: Preliminaries. 1.1. Preface. 1.2. The Domain of Discourse: Routing in VLSI Physical Design. 1.3. Overview of the Book. 1.4. Acknowledgements. 2: Area. 2.1. Introduction. 2.2. Performance Bounds for MST-Based Strategies. 2.3. Iterated 1-Steiner (I1S). 2.4. Enhancing I1S Performance. 2.5. Practical Implementation Options for I1S. 2.6. On the Maximum MST Degree. 2.7. Steiner Trees in Graphs. 3: Delay. 3.1. Preliminaries. 3.2. Geometric Approaches to Delay Minimization. 3.3. Minimization of Actual Delay. 3.4. New Directions. 4: Skew. 4.1. Preliminaries. 4.2. An Early Matching-Based Approach. 4.3. DME: Exact Zero Skew with Minimum Wirelength. 4.4. Planar-Embeddable Trees. 4.5. Remarks. 5: Multiple Objectives. 5.1. Minimum Density Trees. 5.2. Multi-Weighted Graphs. 5.3. Prescribed-Width Routing. A: Appendix: Signal Delay Estimators. A.1. Basics. A.2. Accuracy and Fidelity. References. Author Index. Term Index.
183 citations
Cites background or result from "Performance-driven global routing f..."
...The following variants Hi, H2 and H3 have improved performance over the original BPRIM algorithm [61, 63]....
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...To address both tree radius and tree cost in the routing construction, [61] proposed the following:...
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...[61], whioh was contemporaneous with [57], also observed the existence of conflicting min-cost and min-radius objectives in performance-driven routing....
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01 Jul 1993
TL;DR: It is shown that interconnect topology optimization can be achieved by computing optimal generalized rectilinear Steiner arborescences and an efficient algorithm is presented which yields optimal or near-optimal solutions.
Abstract: In this paper, we study the interconnect design problem under a distributed RC delay model. We study the impact of technology factors on the interconnect designs and present general formulations of the interconnect topology design and wiresizing problems. We show that interconnect topology optimization can be achieved by computing optimal generalized rectilinear Steiner arborescences and we present an efficient algorithm which yields optimal or near-optimal solutions. We reveal several important properties of optimal wire width assignments and present a polynomial time optimal wiresizing algorithm. Extensive experimental results indicate that our approach significantly outperforms other routing methods for high-performance IC and MCM designs. Our interconnect designs reduce the interconnection delays by up to 66% as compared to those by the best known Steiner tree algorithm.
180 citations
Cites methods from "Performance-driven global routing f..."
...In [3, 4], a timing-driven global router was proposed to minimize both the total wire1...
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References
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TL;DR: It is found possible to define delay time and rise time in such a way that these quantities can be computed very simply from the Laplace system function of the network.
Abstract: When the transient response of a linear network to an applied unit step function consists of a monotonic rise to a final constant value, it is found possible to define delay time and rise time in such a way that these quantities can be computed very simply from the Laplace system function of the network. The usefulness of the new definitions is illustrated by applications to low pass, multi‐stage wideband amplifiers for which a number of general theorems are proved. In addition, an investigation of a certain class of two‐terminal interstage networks is made in an endeavor to find the network giving the highest possible gain—rise time quotient consistent with a monotonic transient response to a step function.
1,693 citations
TL;DR: Upper and lower bounds for delay that are computationally simple are presented in this paper and can be used to bound the delay, given the signal threshold, and to certify that a circuit is "fast enough," given both the maximum delay and the voltage threshold.
Abstract: In MOS integrated circuits, signals may propagate between stages with fanout. The exact calculation of signal delay through such networks is difficult. However, upper and lower bounds for delay that are computationally simple are presented in this paper. The results can be used 1) to bound the delay, given the signal threshold, or 2) to bound the signal voltage, given a delay time, or 3) certify that a circuit is "fast enough," given both the maximum delay and the voltage threshold.
857 citations
24 Jun 1990
TL;DR: A novel approach to clock routing that all but eliminates clock skew and yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum feature sizes, and pin distributions on both randomly created and standard industrial benchmarks is presented.
Abstract: Routing techniques for optimizing clock signals in small-cell (e.g., standard-cell, sea-of-gate, etc.) application-specific ICs (ASICs) are addressed. In previously reported works, the routing of a clock net has been performed using ordinary global routing techniques based on a minimum spanning or minimal Steiner tree that have little understanding of clock-routing problems. The authors present a novel approach to the clock-routing that all but eliminates clock skew and yields excellent phase delay results for a wide range of chip sizes, net sizes (pin count), minimum feature sizes, and pin distributions on both randomly created and standard industrial benchmarks. For certain classes of pin distributions a decrease in skew with an increase in net size was proven theoretically and observed experimentally. A two to three order magnitude reduction in skew when compared to a minimum rectilinear spanning tree was observed. >
235 citations
25 Jun 1984
TL;DR: A chip layout procedure for optimizing the performance of critical timing paths in a synchronous digital circuit is presented, which uses the path analysis data produced by a static timing analysis program to generate weights for critical nets on clock and data paths.
Abstract: A chip layout procedure for optimizing the performance of critical timing paths in a synchronous digital circuit is presented. The procedure uses the path analysis data produced by a static timing analysis program to generate weights for critical nets on clock and data paths. These weights are then used to bias automatic placement and routing in the layout program. This approach is shown to bring the performance of the chip significantly closer to that of an ideal layout which is assumed to have no delay due to routing between cells.
175 citations
01 Jun 1989
TL;DR: A novel approach to performance-driven placement is presented, combining timing analysis and physical design to dynamically optimize the performance of the chip during placement.
Abstract: The increasingly important role of the interconnect in the timing performance of present and future integrated circuit technologies underscores the need to reconsider conventional physical design CAD tools, and devise new ways to influence performance during layout. Interconnects are not perfect conductors, they introduce parasitic elements that load the logic gates and distort the temporal properties of the design as viewed by the logic designer. Cell placement that minimizes wirelength as the sole objective does not solve the problem, leaving a margin for performance improvement that has not been fully exploited. This paper presents a novel approach to performance-driven placement, combining timing analysis and physical design to dynamically optimize the performance of the chip during placement. The ideas are embodied in a program named Allegro, and preliminary results tested on Sea-of-Gate designs are encouraging.
173 citations