Performance enhancement in Asymmetric Gate Dielectric MOSFET
01 Dec 2007-pp 417-420
TL;DR: In this paper, the asymmetric gate dielectric (AGD) MOSFET was studied with the help of simulations and the authors showed that the channel electric-field is larger at the source end resulting in higher carrier velocity and smaller at the drain end, resulting in reduced short channel effects.
Abstract: The asymmetric gate dielectric (AGD) MOSFET, where the equivalent dielectric thickness is higher at the source end than at the drain end, is studied with the help of simulations A study of the properties of this device shows that, compared to the symmetric structure, the channel electric-field is larger at the source end resulting in higher carrier velocity and smaller at the drain end resulting in reduced short channel effects The AGD devices show lesser drain induced barrier lowering and higher voltage gain compared to conventional devices, which should be useful for both digital and analog applications The device structure has also been optimized for best performance
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TL;DR: In this paper, the dual material gate (DMG) FET was proposed and demonstrated, where the gate consists of two laterally contacting materials with different work functions, such that the threshold voltage near the source is more positive than that near the drain, resulting in a more rapid acceleration of charge carriers in the channel.
Abstract: A generic new type of field effect transistor (FET), the dual material gate (DMG) FET, is proposed and demonstrated. The gate of the DMGFET consists of two laterally contacting materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel FET, the opposite for p-channel FET), resulting in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects. Using the heterostructure FET as a vehicle, the principle, computer simulation results, design guidelines, processing, and characterization of the DMGFET are discussed in detail.
450 citations
IBM1
TL;DR: Mathematical details of a two-dimensional semiconductor device simulation program are presented and Applicability of the carrier transport model to shallow junction bipolar transistors is discussed.
Abstract: Mathematical details of a two-dimensional semiconductor device simulation program are presented, Applicability of the carrier transport model to shallow junction bipolar transistors is discussed. Use of this program to optimize device structures in new bipolar technology is illustrated by presenting calculated device characteristics for variations in a few selected process conditions, Software links that automatically transfer data from a two-dimensional process simulation program and to a quasi-three-dimensional device equivalent circuit model generation program are also discussed.
194 citations
TL;DR: In this paper, the authors compared the performance of FD dual-material gate (DMG) SOI MOSFETs with their single material gate counterparts and provided an incentive for further experimental exploration.
Abstract: The novel features of a fully depleted (FD) dual-material gate (DMG) silicon-on-insulator (SOI) MOSFET are explored theoretically and compared with those of a compatible SOI MOSFET. The two-dimensional numerical simulation studies demonstrate the novel features as threshold voltage roll-up and simultaneous transconductance enhancement and suppression of short-channel effects offered by the FD DMG SOI MOSFET. Moreover, these unique features can be controlled by engineering the workfunction and length of the gate material. This work illustrates the benefits of high-performance FD DMG SOI MOS devices over their single material gate counterparts and provides an incentive for further experimental exploration.
125 citations
TL;DR: In this paper, a novel hetero-material gate MOSFET intended for integration into the existing deep-submicron silicon technology is proposed and simulated, and it is shown that by adding a layer of material with a larger work function to the source side of the gate, short-channel effects can be greatly suppressed without degrading the driving ability.
Abstract: A novel hetero-material gate MOSFET intended for integration into the existing deep-submicron silicon technology is proposed and simulated. It is shown that by adding a layer of material with a larger workfunction to the source side of the gate, short-channel effects can be greatly suppressed without degrading the driving ability. The threshold voltage roll-off can be compensated and tuned by controlling the length of this second gate. The new structure has great potential in breaking the barrier of deep-suhmicron MOSFET's scaling beyond 0.1 /spl mu/m technologies.
108 citations
01 Dec 1997
TL;DR: The dual material gate field effect transistor (DMGFET) as discussed by the authors is a new type of device, which consists of two laterally contacting materials with different work functions, and it takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain, resulting a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short channel effects.
Abstract: A new type of device, the dual material gate field effect transistor (DMGFET), is presented for the first time The gate of the DMGFET consists of two laterally contacting materials with different work functions This novel gate structure takes advantage of material work function difference in such a way that the threshold voltage near the source is more positive than that near the drain, resulting a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short channel effects
105 citations
"Performance enhancement in Asymmetr..." refers background in this paper
...In 1997, Long et al. [ 5 ] proposed a new device called the dual material gate (DMG) MOSFET to create a field discontinuity in the channel resulting in simultaneous transport enhancement and SCE suppression [6-8]....
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