Performance Investigation of Universal Gates and Ring Oscillator using Doping-free Bipolar Junction Transistor
13 Jun 2020-pp 125-126
TL;DR: In this article, the performance of symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) in universal gates and ring oscillator was investigated.
Abstract: Performance of symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) in universal gates and ring oscillator were investigated. Charge carriers in SOI at emitter and collector regions are induced with two unique approaches, i.e., the charge plasma (CP) and polarity control (PC). Four types of devices (CP-NPN, CP-PNP, PC-NPN, and PC-PNP) was used for bipolar CMOS type NAND and NOR gates. Excellent transient response with rise and fall time less than 5 ns and propagation delay less than 2.4 ns were obtained.
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TL;DR: In this article, a symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) using differential pass transistor logic is presented, and their performance matrices are presented.
Abstract: Logic gates are designed using symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) using differential pass transistor logic, and their performance matrices are presented. Charge carriers are induced in lightly doped emitter and collector regions using two unique approaches. i.e., the charge plasma (CP) and polarity control (PC). AND, OR and XOR gates are designed using four types of devices (CP-NPN, CP-PNP, PC-NPN, and PC-PNP) and transient and noise margin analysis are performed. The transient response shows rise and fall time less than 100 ps while worst-case noise margin of 0.25 V observed for an input voltage of 1 V. Moreover, 2:1 multiplexer is also designed and explored for output transient and voltage levels. The delay of less than 2.2 ns is achieved with a nominal deviation of 0.1 V and 0.04 V for high and low output levels respectively.
2 citations
TL;DR: This study presents a methodology based on unstable dissipative systems of type 1 (UDS-1), a kind of dynamical system capable of generating multi-scrolls and multi-stability and highlights that the selection of the desired logic gate is realized just by varying a couple of parameters.
Abstract: The obtainment of a dynamical logic gate (DLG), which is a device capable of implementing several logic functions using the same model, has been one of the goals of the scientific community. Dynamical systems, specifically those that display chaotic behavior, have been widely used to emulate different logic gates which are the basis of general-purpose computing. In this study, we present a methodology based on unstable dissipative systems of type 1 (UDS-1), a kind of dynamical system capable of generating multi-scrolls and multi-stability. Using these two features, we codify inputs, subsequently, we get the adequate output, developing in this way a dynamical (reconfigurable) logic gate that performs any of the sixteen possible logic functions of two inputs. A highlight of the proposed methodology is that the selection of the desired logic gate is realized just by varying a couple of parameters.
11 Dec 2022
TL;DR: In this article , the performance of thin body doping-free bipolar transistors on SOI is demonstrated for logic gates circuit using differential pass transistor logic, where charge carriers are induced inside the lightly doped SOI layer by using charge plasma (CP) and polarity control (PC) approaches.
Abstract: The performance of thin body doping-free bipolar transistors on SOI are demonstrated for logic gates circuit using differential pass transistor logic. Charge carriers are induced inside the lightly doped SOI layer by using charge plasma (CP) and polarity control (PC) approaches. The study analyzes the transient, power, and noise margins of logic gates i.e., AND, OR and XOR gates designed using four device configurations i.e., CP based npn, CP based pnp, PC based npn, and PC based pnp. The results of these analyses are compared to prior studies of doping-free device-based circuits. The transient analysis indicates rise and fall time less than 50 ps and average switching power less than 5 µ W. The worstcase noise margin observed for 1 V input level is 0.28 V. Additionally, a 2:1 multiplexer is also designed and examined for response time and output voltage levels. For high logic, worst case output was 0.88 V, while for low logic, it was 0.05 V. The multiplexer took less than 1.8 ns to produce the output.
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TL;DR: In this paper, the authors introduce a versatile nanoscale transistor that provides identical BJT behavior and expands its capabilities, using CMOS fabrication technology and creating BJT emitter, base, and collector via electric fields.
Abstract: Nano-electronic integrated circuit technology is exclusively based on MOSFET transistor due to its scalability down to the nanometer range. On the other hand, Bipolar Junction Transistor (BJT), which provides unmatched analog characteristics and frequency response, cannot be scaled to nanometer regime without the loss of transistor action. Here a versatile nanoscale transistor is introduced that provides identical BJT behavior and expands its capabilities. The new transistor uses CMOS fabrication technology and creates BJT emitter, base, and collector via electric fields. By allowing carrier modulation during operation, its current gain can be changed at least by five orders of magnitude. This property introduces novel adaptive, variable gain, and programmable analog modules into existing electronic circuit design and manufacturing. A NOT gate version of this device with the critical dimension of 7 nm operates at 730 GHz, and its three-stage ring oscillator exhibits a frequency of 240 GHz. With proper gate biasing, it can also operate as a nanoscale MOSFET, easily alleviating short-channel effects.