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Journal ArticleDOI

Periodically Swapping Modulation (PSM) Strategy for Three-Level (TL) DC/DC Converters With Balanced Switch Currents

01 Jan 2018-IEEE Transactions on Industrial Electronics (IEEE)-Vol. 65, Iss: 1, pp 412-423
TL;DR: A novel periodically swapping modulation (PSM) strategy is proposed for balancing the power switches’ currents in various types of TL dc/dc converters, which guarantees that the currents through the power switch pairs are kept balanced in every two switching periods.
Abstract: The asymmetrical modulation strategy is widely used in various types of three-level (TL) dc/dc converters, while the current imbalance among the power switches is one of the important issues. In this paper, a novel periodically swapping modulation (PSM) strategy is proposed for balancing the power switches’ currents in various types of TL dc/dc converters. In the proposed PSM strategy, the driving signals of the switch pairs are swapped periodically, which guarantees that the currents through the power switches are kept balanced in every two switching periods. Therefore, the proposed PSM strategy can effectively improve the reliability of the converter by balancing the power losses and thermal stresses among the power switches. The operation principle and performances of the proposed PSM strategy are analyzed in detail. Finally, the simulation and experimental results are presented to verify the proposed modulation strategy.

Summary (2 min read)

Introduction

  • Widely used in various types of three-level (TL) DC/DC converters, while the current imbalance among the power switches is one of the important issues.
  • The analysis of other types of TL DC/DC converters [13-16] under the proposed modulation strategy is similar to that of the four-switch TL DC/DC converter.
  • This stage would finish until that the voltage on Cs2 increases to Vin/2 and the voltage on Cs1 decreases to 0 V. During this stage, the primary current ip would increase linearly and flow through Lr, Tr, Cb, S4, C1, C2, and S1 as shown in Fig. 3(d).
  • In the proposed PSM strategy shown in Fig. 2, the driving signals of the power switches in the first switching period and driving signals of the power switches in the second switching period can be regarded as two separate modulation modes named mode I and II.

C. Currents through Primary Power Switches

  • Normally, there are mainly two types of widely used power switches in the industrial applications, which are MOSFET and IGBT for the low power and high power applications respectively.
  • The theoretical waveforms of the currents i1, i2, i3, and i4 under the conventional and proposed modulation strategy shown in Fig. 1(b) and Fig. 2 would be the same whether MOSFET or IGBT is used.

D. Currents and Voltages on Two Input Capacitors

  • In order to simplify the following analysis, one assumption is made that the input current iin is constant due to the effect from the output inductance of the input power supplier and inductance of the input line.
  • Therefore, the maximum voltage ripples on the two input capacitor (V1, V2) in the steady operations are the same under the conventional and proposed modulation strategy because the proposed PSM strategy operates by swapping the modulation mode I (first switching period) and II (second switching period).

E. ZVS Achievement Conditions

  • In the first switching period, in order to ensure S3 or S4 realizing zero-voltage switch-on, the energy E1 is needed to fully discharge the parasitic capacitor of the in-coming switch and charge the parasitic capacitor of the out-going switch, whose expression can be given by (15).
  • The energy to achieve zero-voltage switch-on for S3 and S4 is provided by both the output filter inductance and leakage inductance of the transformer.
  • Normally, the output filter inductance is large enough to realize the zero-voltage switch-on for S3 and S4 even at light load.
  • In order to achieve the zero-voltage switch-on of S1 or S2, the energy E2 should satisfy the requirement (16) to fully discharge the parasitic capacitor of the in-coming switch and charge the parasitic capacitor of the out-going switch.
  • The requirements to achieve ZVS in the second switching period is similar to that in the first switching period, which is not repeated here.

F. Duty Cycle Limitation and Dead time Design

  • In the proposed PSM strategy, the duty ratio d1 shown in Fig. 2 should be smaller than 0.5 minus dead time to avoid the short connection of C1 and C2 via conducting the switch pairs (S1, S2) and (S3, S4) simultaneously.
  • In addition, The dead time Tdead of the switch pairs (S1, S2) and (S3, S4) must be also set in the real applications to avoid the short connection of C1 and C2 via conducting the switch pairs (S1, S2) and (S3, S4) simultaneously, whose value can be calculated by (17) if neglecting the parasitic capacitor of the transformer [27].

A. Simulation Verification

  • A simulation model is built in PLECS to verify the proposed PSM strategy.
  • Fig. 4 shows the simulation results under the conventional and proposed modulation strategy, respectively.
  • The RMS values of the currents i1 and i3 are 25.7 A, and the RMS values of the currents i2 and i4 are 49.3 A under the conventional modulation strategy as shown in Fig. 4(a).

B. Experimental Verification

  • In order to verify the proposed PSM strategy, a 1 kW experimental prototype is established.
  • Based on the experimental results shown in Fig. 10, it can be concluded that the current imbalance among the power switches caused by the conventional asymmetrical modulation strategy can be eliminated by utilizing the proposed modulation strategy.
  • Finally, the simulation and experimental results verify the effectiveness and feasibility of the proposed modulation strategy.

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Aalborg Universitet
Periodically Swapping Modulation (PSM) Strategy for Three-Level (TL) DC/DC
Converters With Balanced Switch Currents
Liu, Dong; Deng, Fujin; Zhang, Qi; Chen, Zhe
Published in:
IEEE Transactions on Industrial Electronics
DOI (link to publication from Publisher):
10.1109/TIE.2017.2714125
Publication date:
2018
Document Version
Accepted author manuscript, peer reviewed version
Link to publication from Aalborg University
Citation for published version (APA):
Liu, D., Deng, F., Zhang, Q., & Chen, Z. (2018). Periodically Swapping Modulation (PSM) Strategy for Three-
Level (TL) DC/DC Converters With Balanced Switch Currents. IEEE Transactions on Industrial Electronics,
65(1), 412-423. [7946257]. https://doi.org/10.1109/TIE.2017.2714125
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
Abstract The asymmetrical modulation strategy is
widely used in various types of three-level (TL) DC/DC
converters, while the current imbalance among the power
switches is one of the important issues. In this paper, a
novel periodically swapping modulation (PSM) strategy is
various types of TL DC/DC converters. In the proposed
PSM strategy, the driving signals of the switch pairs are
swapped periodically, which guarantees that the currents
through the power switches are kept balanced in every
two switching periods. Therefore, the proposed PSM
strategy can effectively improve the reliability of the
converter by balancing the power losses and thermal
stresses among the power switches. The operation
principle and performances of the proposed PSM strategy
are analyzed in detail. Finally, the simulation and
experimental results are presented to verify the proposed
modulation strategy.
Index Terms DC/DC converter, periodically swapping
modulation (PSM), three-level (TL).
I. INTRODUCTION
he three-level (TL) DC/DC converter is attractive for the
high input voltage applications [1-5] because the power
switches only need to withstand half of the input voltage in the
TL DC/DC converter. In [6], the TL circuit structure was
firstly applied into the DC/DC converter. Based on the
conventional TL DC/DC converter in [6], many studies about
the TL DC/DC converter have been carried out [7-12]. In [7],
a zero-voltage and zero-current switching TL DC/DC
converter was proposed, in which a flying capacitor in the
primary side was added to make the phase-shift control
strategy applicable in the TL DC/DC converter. Based on [7],
an auxiliary circuit was added in the secondary side to reduce
Manuscript received December 22, 2016; revised March 06, 2017,
April 06, 2017, and April 25, 2017; accepted May 24, 2017.
Dong Liu, and Zhe Chen are with the Department of Energy
Technology, Aalborg University, Aalborg, 9220 Denmark (email:
dli@et.aau.dk, zch@et.aau.dk).
Fujin Deng is with the School of Electrical Engineering, Southeast
University, Nanjing, 210000 China (email: dfjqfa@163.com).
Qi Zhang is with the Department of Electrical Engineering, Xi'an
(email:
zhangqi_hero@163.com).
the circulating current [8]. A new TL DC/DC converter
composed of one TL leg and one two-level leg was proposed
in [9] for the high power applications. Reference [10]
proposed a zero-voltage switching (ZVS) DC/DC converter
with two TL circuits sharing the same power switches, which
can reduce the current stresses on the transformer windings
and output rectifiers. In [11], a zero-voltage and zero current-
switching TL DC/DC converter combining a TL converter and
full-bridge converter was proposed to reduce the output filter
inductance. In addition, a hybrid TL DC/DC converter
composed of a full-bridge TL converter and a half-bridge TL
converter was proposed to extend the ZVS range in [12]. In
order to achieve soft switching for the conv
improvement, the phase-shift control strategy is utilized in the
above various types of TL D/DC converters [6-12].
The asymmetrical modulation strategy is another
modulation strategy, which is also widely used in various
types of TL DC/DC converters [13-16]. In [13], a TL DC/DC
converter based on the flying capacitor was proposed, which
features with the simple and compact circuit structure. A new
TL DC/DC converter with two transformers was proposed in
[14] to reduce the current stresses on the transformer
windings. Reference [15] proposed a dual half-bridge
cascaded TL DC/DC converter, which is composed of two
half-bridge cells and two transformers. In addition, a novel
four-switch TL DC/DC converter was proposed in [16], which
only adds one DC-blocking capacitor but removes two
clamped diodes in comparison with the conventional TL
DC/DC converter [6]. The asymmetrical modulation strategy
realizes the soft switching for the above various types of TL
DC/DC converters [13-16]. However, there is one important
issue about the conventional asymmetrical modulation
strategy that the currents through the primary power switches
are imbalanced.
Many studies have been carried recently on the TL DC/DC
converters, which mainly focus on the topics of extending the
soft switching range [17], [18], reducing the circulating
currents [19], and balancing the voltages on the input
capacitors [20], [21]. However, until now there are few studies
discussing about such current imbalance of the primary power
switches in the TL DC/DC converters under the conventional
asymmetrical modulation strategy, which would affect the
reliability of the converter by causing the power loss
-
Dong Liu, Student Member, IEEE, Fujin Deng, Member, IEEE, Qi Zhang, Member, IEEE
and Zhe Chen, Senior Member, IEEE
T

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
imbalance and thermal stress imbalance among the power
switches [22], [23].
In this paper, a novel periodically swapping modulation
(PSM) strategy is proposed, which can be used for various
types of TL DC/DC converter to balance the currents flowing
through the power switches. In the proposed modulation
strategy, the driving signals of the switch pairs are swapped
periodically
balanced in every two switching periods. Consequently, the
proposed modulation strategy can balance the power losses
and thermal stresses among the power switches in the TL
DC/DC converter, which can thus improve the reliability of
the TL DC/DC converter. In this paper, the four-switch TL
DC/DC converter [16] as shown in Fig. 1(a) is selected as a
sample to analyze the operation principle and performances of
the proposed PSM strategy. The analysis of other types of TL
DC/DC converters [13-16] under the proposed modulation
strategy is similar to that of the four-switch TL DC/DC
converter.
This paper is organized as follows. Section II analyzes the
issue under the
conventional modulation strategy. Section III introduces the
operation principle of the proposed PSM strategy. Section IV
analyzes the characteristics and performances of the four-
switch TL DC/DC converter under the proposed modulation
strategy in detail. Section V presents the simulation and
experimental results to verify the effectiveness and feasibility
of the proposed modulation strategy. Finally, the main
contributions are summarized in Section VI.
II. CURRENT IMBALANCE ANALYSIS UNDER
CONVENTIONAL ASYMMETRICAL MODULATION
STRATEGY
Figs. 1(a) and 1(b) show the circuit structure of the four-
switch TL DC/DC converter and conventional asymmetrical
modulation strategy with the main operation waveforms,
respectively. In Fig. 1(a), two input capacitors C
1
and C
2
are
used to split the input voltage V
in
into two voltages V
1
and V
2
;
S
1
- S
4
and D
1
- D
4
are primary power switches and diodes; T
r
is the high frequency transformer; L
r
is the leakage inductance
of T
r
; C
s1
- C
s4
are the parasitic capacitors of S
1
- S
4
; C
b
is the
DC-blocking capacitor in the primary side. In the secondary
side, there are four rectifier diodes D
r1
- D
r4
, one output filter
inductor L
o
, and one output filter capacitor C
o
. In Fig. 1(a), i
p
is the primary current of the transformer T
r
; i
1
, i
2
, i
3
, and i
4
are
the currents through the primary power devices (S
1
, D
1
), (S
2
,
D
2
), (S
3
, D
3
), and (S
4
, D
4
); i
in
is the input current; i
c1
and i
c2
are
the currents flowing through the two input capacitors C
1
and
C
2
; i
Lo
is the current through L
o
; V
cb
is the voltage on the DC-
blocking capacitor C
b
; i
o
and V
o
are the output current and
output voltage; V
ab
is the voltage between point a and b; n is
the turns ratio of the transformer T
r
. In Fig. 1(b), d
rv1
- d
rv4
are
four driving signals of the power switches S
1
- S
4
, where (S
1
,
S
2
) and (S
3
, S
4
) are complementary switch pairs; d
1
and d
2
are
duty ratios in one switching period and d
2
is 1 - d
1
if
neglecting the dead time. From Fig. 1(b), it can be seen that
the currents (i
1
, i
3
) and (i
2
, i
4
) are different because d
2
is larger
than d
1
, which would result in the power loss imbalance and
thermal stress imbalance among the primary power switches.
(a)
(b)
Fig. 1. (a) Circuit Structure of four-switch TL DC/DC converter. (b)
Conventional asymmetrical modulation strategy [16] with main
operation waveforms.
In order to simplify the analysis about the currents through
the four power switches in the four-switch TL DC/DC
converter, several assumptions are made that: 1) the
inductance of the output filter inductor L
o
is large enough to be
considered as a current source; 2) the power switches S
1
- S
4
and diodes D
1
- D
4
are ideal; 3) the two input capacitors and
DC-blocking capacitor are large enough to be regarded as the
constant voltage sources with the value of V
in
/2.
From Fig. 1(b), it can be seen that the current pairs (i
1
, i
3
)
and (i
2
, i
4
) are the same respectively in every switching period.
Therefore, only the expressions of the currents i
1
and i
2
in one
switching period are given as
2 5
1
5 6
[ - ]
2
[ - ]
o in
r
o
i V
t t t
n L
i
i
t t
n
(1)
V
in
T
r
D
r1
D
r2
D
r4
D
r3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
o
V
cb
D
1
C
s1
D
2
C
s2
D
3
C
s3
D
4
C
s4
L
r
n:1
V
ab
V
pri
i
1
i
2
i
3
i
4
i
in
i
c1
i
c2
t
0
1
V
in
/2
t
V
in
V
ab
t
0
1
i
p
t
|i
o
/n|
|i
o
/n|
t
i
2
t
i
1
i
o
/n
t
0
t
1
t
2
t
3
t
4
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
5
d
rv
4
d
rv
3
d
1
T
s
d
rv
4
d
rv
3
d
1
T
s
d
rv
1
d
rv
2
d
rv
1
d
rv
2
d
2
T
s
i
3
i
4
-i
o
/n
i
o
/n
-i
o
/n
i
o
/n
-i
o
/n
i
o
/n
-i
o
/n
t
t
d
2
T
s
t
i
c
1
|
i
in
|
|i
o
/n
|-|
i
in
|
|
i
in
|
+
|
i
o
/n
|
t
|
i
in
|
i
c
2
|
i
in
|
+
|
i
o
/n
|
|i
o
/n
|-|
i
in
|

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
0 2
6 8
2
8 11
11 12
[ - ]
[ - ]
[ - ]
2
[ - ]
o
o
o in
r
o
i
t t
n
i
t t
n
i V
t t t
n L
i
t t
n
i
(2)
According to (1) and (2), the root mean square (RMS)
values of the currents i
1
, i
2
, i
3
, and i
4
under the conventional
asymmetrical modulation strategy namely i
1_rms_c
, i
2_rms_c
,
i
3_rms_c
, and i
4_rms_c
can be calculated by
2 3
1
2 3
1_ _ 3_ _
8
3
o r o
in s
rms c rms c
i L i
d
n n V T
i i (3)
2 3
2
2 3
2 _ _ 4 _ _
8
3
o r o
in s
rms c rms c
i L i
d
n n V T
i i (4)
From (3) and (4), it can be observed that the RMS values of
(i
1
, i
3
) and (i
2
, i
4
) are different because d
1
and d
2
are normally
different in the asymmetrical modulation strategy [24-26].
This current imbalance would result in the power loss
imbalance and thermal stress imbalance among the primary
reliability.
III. PROPOSED PERIODICALLY SWAPPING MODULATION
STRATEGY
The PSM strategy is proposed for various types of TL
DC/DC converters, where the driving signals of the switch
pairs are swapped periodically in order to balance the power
. Fig. 2 shows the proposed PSM for the
four-switch TL DC/DC converter configuration, where the
main operation waveforms are presented.
The proposed PSM strategy operates by swapping the
driving signals of the switching pairs (S
1
, S
4
) and (S
2
, S
3
)
respectively in every switching period to make the currents
flowing through the four power switches balanced in every
two switching periods as shown in Fig. 2, which means that 1)
in the first switching period, the duty ratios of d
rv1
and d
rv3
are
both 0.5 if neglecting the dead time, the duty ratios of d
rv2
and
d
rv4
are both d
1
; and 2) in the second switching period, the
duty ratios of d
rv2
and d
rv4
are both 0.5 if neglecting the dead
time, the duty ratios of d
rv1
and d
rv3
are both d
1
. In the real
applications, the output voltage V
o
is controlled by adjusting
the duty ratio d
1
. In the first switching period, the calculated d
1
is set for the driving signals of the power switches S
2
and S
4
and duty ratio 0.5 minus the dead time is set for the driving
signals of the power switches S
1
and S
3
in the first switching
period; contrarily the calculated d
1
is set for the driving signals
of the power switches S
1
and S
3
and duty ratio 0.5 minus the
dead time is set for the driving signals of the power switches
S
2
and S
4
in the second switching period. The duty ratio d
1
calculated by the control loop would be changed in every two
switching periods to adjust the output voltage V
o
in the steady
operations.
Fig. 3 shows the equivalent circuits to explain the operation
principle of the proposed PSM strategy presented in Fig. 2.
Stage 1 [before t
2
] Before t
2
, the circuit works at a free-
wheeling mode with the primary current i
p
flowing through L
r
,
S
2
, C
2
, D
4
, C
b
, and T
r
as shown in Fig. 3(a). During this stage,
the primary current i
p
is kept at -i
o
/n. The currents on (S
1
, D
1
)
and (S
3
, D
3
), which are i
1
and i
3
, are both 0 A.
Stage 2 [t
2
- t
3
] At t
2
, the switch S
2
is turned off. Then, the
capacitor C
s2
starts to charge, and the capacitor C
s1
begins to
discharge. This stage would finish until that the voltage on C
s2
increases to V
in
/2 and the voltage on C
s1
decreases to 0 V. In
addition, the primary current i
p
begins to increase, and there is
no enough primary power to provide the output power, so the
four output rectifier diodes D
r1
- D
r4
conduct simultaneously.
Fig. 2. Proposed periodically swapping modulation (PSM) strategy with main operation waveforms.
d
rv2
d
rv
1
0
1
V
in
V
ab
d
rv
4
d
rv3
0
1
i
p
|i
o
/n|
|i
o
/n|
i
1
i
2
d
1
T
s
d
1
T
s
V
in
/2
T
s
t
t
t
t
t
t
d
rv
4
d
rv
1
T
s
First Switching Period Second Switching Period
d
rv
1
d
rv3
d
1
T
s
d
1
T
s
d
rv
4
d
rv2
d
rv
2
d
rv
3
-i
o
/n
i
o
/n
i
3
i
4
t
t
i
o
/n
-i
o
/n
i
o
/n
-i
o
/n
i
o
/n
i
o
/n
i
o
/n
-i
o
/n
i
o
/n
-i
o
/n
i
o
/n
-i
o
/n
i
o
/n
-i
o
/n
i
o
/n
-i
o
/n
-i
o
/n
d
loss
T
s
d
loss
T
s
d
loss
T
s
d
loss
T
s
d
loss
T
s
V
in
V
in
V
in
/2
i
o
/n
-i
o
/n
t
0
t
1
t
2
t
3
t
4
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
5
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
i
c
1
|
i
in
|
|
i
in
|
+
|
i
o
/n
|
|i
o
/n
|-|
i
in
|
i
c
2
|
i
in
|
|
i
in
|
+
|
i
o
/n
|
|i
o
/n
|-|
i
in
|
t
t

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS
(a) (b) (c)
(d) (e) (f)
(g) (h) (i)
(j) (k) (l)
(m)
Fig. 3. Equivalent circuits in the first switching period. (a) [before t2]. (b) [t2 - t3]. (c) [t3 - t5]. (d) [t5 - t6]. (e) [t6 - t7]. (f) [t7 - t8]. (g) [t8 - t9]. (h) [t9 -
t10]. (i) [t10 - t12]. (j) [t12 - t13]. (k) [t13 - t14]. (l) [t14 - t15]. (m) [t15 - t16].
Stage 3 [t
3
- t
5
] At t
3
, the voltage on C
s1
decreases to 0 V,
then the diode D
1
begins to conduct. Therefore, the switches S
1
and S
4
can be turned on at zero-voltage at the time t
4
. The
primary current i
p
would flow through L
r
, D
1
, C
1
, C
2
, D
4
, C
b
,
and T
r
.
Stage 4 [t
5
- t
6
] At t
5
, the primary current i
p
increases to 0 A,
then the direction of i
p
begins to change. During this stage, the
primary current i
p
would increase linearly and flow through L
r
,
T
r
, C
b
, S
4
, C
1
, C
2
, and S
1
as shown in Fig. 3(d).
Stage 5 [t
6
- t
7
] At t
6
, the primary current i
p
increases to i
o
/n,
then D
r2
and D
r3
turn off and the input power begins to be
transferred to the output through T
r
, D
r1
, and D
r4
. During this
stage, the primary current i
p
would be kept at i
o
/n; the currents
i
1
and i
4
are both i
o
/n; and the currents i
2
and i
3
are both 0 A.
Stage 6 [t
7
- t
8
] At t
7
, the switch S
4
is turned off. The
capacitor C
s4
starts to charge, and the capacitor C
s3
begins to
discharge. This stage would finish until the voltage on C
s4
increases to V
in
/2 and the voltage on C
s3
decreases to 0 V.
Stage 7 [t
8
- t
9
] At t
8
, the voltage on C
s3
decreases to 0 V,
then the diode D
3
begins to conduct. During this stage, the
circuit operates at a free-wheeling mode with the primary
current i
p
flowing through L
r
, T
r
, C
b
, D
3
, C
1
, and S
1
as shown
in Fig. 3(g).
Stage 8 [t
9
- t
10
] At t
9
, the switch S
1
is turned off. Then, the
capacitor C
s1
starts to charge, and the capacitor C
s2
begins to
discharge. This stage would finish until that the voltage on C
s1
increases to V
in
/2 and the voltage on C
s2
decreases to 0 V. The
primary current i
p
starts to decrease, and there is no enough
primary power to provide the output power, so the four output
rectifier diodes D
r1
- D
r4
conduct simultaneously.
V
in
T
r
D
r
1
D
r
2
D
r
4
D
r
3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
V
o
V
cb
D
1
C
s
1
D
2
C
s
2
D
3
C
s
3
D
4
C
s
4
L
r
V
in
T
r
D
r
1
D
r
2
D
r
4
D
r
3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
V
o
V
cb
D
1
C
s
1
D
2
C
s
2
D
3
C
s
3
D
4
C
s
4
L
r
V
in
T
r
D
r
1
D
r
2
D
r
4
D
r
3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
V
o
V
cb
D
1
C
s
1
D
2
C
s
2
D
3
C
s
3
D
4
C
s
4
L
r
V
in
T
r
D
r
1
D
r
2
D
r
4
D
r
3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
V
o
V
cb
D
1
C
s
1
D
2
C
s
2
D
3
C
s
3
D
4
C
s
4
L
r
V
in
T
r
D
r
1
D
r
2
D
r
4
D
r
3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
V
o
V
cb
D
1
C
s
1
D
2
C
s
2
D
3
C
s
3
D
4
C
s
4
L
r
V
in
T
r
D
r
1
D
r
2
D
r
4
D
r
3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
V
o
V
cb
D
1
C
s
1
D
2
C
s
2
D
3
C
s
3
D
4
C
s
4
L
r
V
in
T
r
D
r1
D
r2
D
r4
D
r3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
V
o
V
cb
D
1
C
s1
D
2
C
s2
D
3
C
s3
D
4
C
s4
L
r
V
in
T
r
D
r1
D
r2
D
r4
D
r3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
L o
V
1
V
2
i
o
V
o
V
cb
D
1
C
s1
D
2
C
s2
D
3
C
s3
D
4
C
s4
L
r
V
in
T
r
D
r1
D
r2
D
r4
D
r3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
V
o
V
cb
D
1
C
s1
D
2
C
s2
D
3
C
s3
D
4
C
s4
L
r
V
in
T
r
D
r1
D
r2
D
r4
D
r3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
V
o
V
cb
D
1
C
s1
D
2
C
s2
D
3
C
s3
D
4
C
s4
L
r
V
in
T
r
D
r1
D
r2
D
r4
D
r3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
L o
V
1
V
2
i
o
V
o
V
cb
D
1
C
s1
D
2
C
s2
D
3
C
s3
D
4
C
s4
L
r
V
in
T
r
D
r1
D
r2
D
r4
D
r3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
Lo
V
1
V
2
i
o
V
o
V
cb
D
1
C
s1
D
2
C
s2
D
3
C
s3
D
4
C
s4
L
r
V
in
T
r
D
r1
D
r2
D
r4
D
r3
S
1
S
2
S
3
S
4
C
b
C
1
C
2
L
o
C
o
a
b
i
p
i
L o
V
1
V
2
i
o
V
o
V
cb
D
1
C
s1
D
2
C
s2
D
3
C
s3
D
4
C
s4
L
r

Citations
More filters
Journal ArticleDOI
TL;DR: A new pulsewidth modulation (PWM) methodology for loss balance in grid connected PV single-phase five-level inverters is presented, based on swapping the utilization of power switches through half or quarter of the fundamental line period based on the redundancies between the switching states in MLIs.
Abstract: Multilevel inverters (MLIs) have proven superior performance in several applications, especially in photovoltaic (PV) applications. However, power switches in MLIs possess high failure rates due to unequal power losses distributions that shorten lifetime of the whole PV inverter. Therefore, a new pulsewidth modulation (PWM) methodology for loss balance in grid connected PV single-phase five-level inverters is presented in this paper. The proposed loss balance PWM (LBPWM) method is based on swapping the utilization of power switches through half or quarter of the fundamental line period based on the redundancies between the switching states in MLIs. In addition, the proposed LBPWM method achieves natural balance among voltages over the dc-link capacitors. The effectiveness and feasibility of the proposed LBPWM method are verified using the simulation environment and experimental prototype. Different operating conditions and points of PV inverters are investigated in addition to reliability evaluation of the PV inverter are provided. Moreover, the superior performance criterion of the proposed LBPWM methods are verified through comprehensive comparisons with the most prominent previously developed PWM methods in the literature. The generalization and implementation steps of the proposed LBPWM method are also provided.

32 citations


Cites background from "Periodically Swapping Modulation (P..."

  • ...in the area of dc/dc converter [6], [21]....

    [...]

  • ...The increased failure rates of the power switches are due to dissimilar distribution of the power losses between devices [5], [6]....

    [...]

Proceedings ArticleDOI
14 Jun 2021
TL;DR: In this article, a novel three-level phase-shift modulation is proposed for serial half bridge (SHB) LLC resonant converter, which is capable of balancing current stress for all switches to realize balanced thermal stress and their longer lifetime.
Abstract: In this paper, a novel three-level phase-shift modulation is proposed for serial half bridge (SHB) LLC resonant converter. The proposed modulation is capable of balancing current stress for all switches to realize balanced thermal stress and their longer lifetime. The operation principle of the proposed modulation strategy is presented and analyzed in detail. ZVS conditions are discussed in different operation modes to ensure high efficiency operation in the entire load range. In addition, the proposed three-level phase-shift modulation provides additional gain range to conventional two level modulations with variable switching frequency control so that very wide output/input voltage range can be achieved. The performance of the proposed modulation is experimentally verified on a 7.5 kW SHB LLC DC/DC converter prototype.

12 citations

Proceedings ArticleDOI
15 Mar 2020
TL;DR: In this article, the authors present control methods that achieve DC-link capacitor voltage balance of a series half bridge (SHB) LLC resonant converter operating at different modulation schemes.
Abstract: This paper presents control methods that achieve DC-link capacitor voltage balance of a series half bridge (SHB) LLC resonant converter operating at different modulation schemes The principle of the proposed balancing control method is analyzed and studied based on six normally used operation modes of the SHB LLC converter DC-link capacitor voltage balancing strategies are developed separately for two common modulation schemes in SHB topology The performance of the proposed voltage balancing control method is experimentally verified on a 75-kW SHB LLC DC/DC converter prototype under different operating conditions

6 citations


Cites background from "Periodically Swapping Modulation (P..."

  • ...For example, [12] mainly focuses on phase-shift modulation control that is suitable for wide input voltage applications, and [13] focuses on balancing control of the currents flowing through the power switches....

    [...]

DOI
TL;DR: In this article , the authors proposed the concept of monopolar fault reconfiguration for bipolar dc distribution system realized with Bipolar Half Bridge (BiHB) converter, which achieved mode switching by reconfiguring the converter switching pattern.
Abstract: This article proposed the concept of monopolar fault reconfiguration for bipolar dc distribution system realized with Bipolar Half Bridge (BiHB) converter. Monopolar fault reconfiguration oriented from bipolar high voltage direct current (HVdc) transmission grid. For dc distribution, the operation aim is to provide uninterrupted power supply to critical load under monopolar fault. It requires interfacing circuit with fault-tolerant capability as well as control design considering both bipolar and monopolar working mode. The proposed BiHB converter achieves mode switching by reconfiguring the converter switching pattern. Considering both monopolar and bipolar working mode, a bipolar modulation method is proposed for coordinate circuit design. Key influence factors relating to the transient voltage spikes have been identified, including the fault detection delay and the modulation method. Besides, to suppress the voltage spikes caused by monopolar fault, feed-forward compensation is adopted for smooth mode transition. The proposed BiHB converter and control strategy have been comparatively evaluated under fault protection and restoration. Uninterrupted power supply of load has been attained, in validation of the proposed monopolar fault reconfiguration concept.

4 citations

Journal ArticleDOI
TL;DR: In this article , the authors proposed the concept of monopolar fault reconfiguration for bipolar dc distribution system realized with Bipolar Half Bridge (BiHB) converter, which achieved mode switching by reconfiguring the converter switching pattern.
Abstract: This article proposed the concept of monopolar fault reconfiguration for bipolar dc distribution system realized with Bipolar Half Bridge (BiHB) converter. Monopolar fault reconfiguration oriented from bipolar high voltage direct current (HVdc) transmission grid. For dc distribution, the operation aim is to provide uninterrupted power supply to critical load under monopolar fault. It requires interfacing circuit with fault-tolerant capability as well as control design considering both bipolar and monopolar working mode. The proposed BiHB converter achieves mode switching by reconfiguring the converter switching pattern. Considering both monopolar and bipolar working mode, a bipolar modulation method is proposed for coordinate circuit design. Key influence factors relating to the transient voltage spikes have been identified, including the fault detection delay and the modulation method. Besides, to suppress the voltage spikes caused by monopolar fault, feed-forward compensation is adopted for smooth mode transition. The proposed BiHB converter and control strategy have been comparatively evaluated under fault protection and restoration. Uninterrupted power supply of load has been attained, in validation of the proposed monopolar fault reconfiguration concept.

4 citations

References
More filters
Proceedings ArticleDOI
08 Oct 1995
TL;DR: This paper presents three multilevel voltage source converters: (1) diode-clamp, (2) flying-capacitors, and (3) cascaded-inverters with separate DC sources.
Abstract: Multilevel voltage source converters are emerging as a new breed of power converter options for high-power applications. The multilevel voltage source converters typically synthesize the staircase voltage wave from several levels of DC capacitor voltages. One of the major limitations of the multilevel converters is the voltage unbalance between different levels. The techniques to balance the voltage between different levels normally involve voltage clamping or capacitor charge control. There are several ways of implementing voltage balance in multilevel converters. Without considering the traditional magnetic coupled converters, this paper presents three recently developed multilevel voltage source converters: (1) diode-clamp, (2) flying-capacitors, and (3) cascaded-inverters with separate DC sources. The operating principle, features, constraints, and potential applications of these converters are discussed.

3,232 citations


"Periodically Swapping Modulation (P..." refers background or methods or result in this paper

  • ...The analysis of other types of TL dc/dc converters [13]–[16] under the proposed modulation strategy is similar to that of the four-switch TL dc/dc converter....

    [...]

  • ...The asymmetrical modulation strategy is another modulation strategy, which is also widely used in various types of TL dc/dc converters [13]–[16]....

    [...]

  • ...In [13], a TL dc/dc converter based on the flying capacitor was proposed, which features with the simple and compact circuit structure....

    [...]

  • ...The asymmetrical modulation strategy realizes the soft switching for the above-mentioned various types of TL dc/dc converters [13]–[16]....

    [...]

Journal ArticleDOI
TL;DR: A loss-balancing scheme is introduced, enabling a substantially increased output power and an improved performance at zero speed, compared to the conventional NPC VSC.
Abstract: The three-level neutral-point-clamped voltage-source converter (NPC VSC) is widely used in high-power medium-voltage applications. The unequal loss distribution among the semiconductors is one major disadvantage of this popular topology. This paper studies the loss distribution problem of the NPC VSC and proposes the active NPC VSC to overcome this drawback. The switch states and commutations of the converter are analyzed. A loss-balancing scheme is introduced, enabling a substantially increased output power and an improved performance at zero speed, compared to the conventional NPC VSC.

690 citations


"Periodically Swapping Modulation (P..." refers background in this paper

  • ...cal modulation strategy, which would affect the reliability of the converter by causing the power loss imbalance and thermal stress imbalance among the power switches [22], [23]....

    [...]

Journal ArticleDOI
TL;DR: The performance of power electronic systems, especially in terms of efficiency and power density, has continuously improved by the intensive research and advancements in circuit topologies, control schemes, semiconductors, passive components, digital signal processors, and system integration technologies.
Abstract: A new era of power electronics was created with the invention of the thyristor in 1957. Since then, the evolution of modern power electronics has witnessed its full potential and is quickly expanding in the applications of generation, transmission, distribution, and end-user consumption of electrical power. The performance of power electronic systems, especially in terms of efficiency and power density, has been continuously improved by the intensive research and advancements in circuit topologies, control schemes, semiconductors, passive components, digital signal processors, and system integration technologies.

689 citations


"Periodically Swapping Modulation (P..." refers background in this paper

  • ...cal modulation strategy, which would affect the reliability of the converter by causing the power loss imbalance and thermal stress imbalance among the power switches [22], [23]....

    [...]

Journal ArticleDOI
TL;DR: In this article, a zero-voltage and zero-current switching (ZVZCS) three-level DC/DC converter is presented, which uses a phase shift control with a flying capacitor in the primary side to achieve ZVS for the outer switches.
Abstract: This paper presents a novel zero-voltage and zero-current switching (ZVZCS) three-level DC/DC converter. This converter overcomes the drawbacks presented by the conventional zero-voltage switching (ZVS) three-level converter, such as high circulating energy, severe parasitic ringing on the rectifier diodes, and limited ZVS load range for the inner switches. The converter presented in this paper uses a phase-shift control with a flying capacitor in the primary side to achieve ZVS for the outer switches. Additionally, the converter uses an auxiliary circuit to reset the primary current during the freewheeling stage to achieve zero-current switching (ZCS) for the inner switches. The principle of operation and the DC characteristics of the new converter are analyzed and verified on a 6 kW, 100 kHz experimental prototype.

258 citations


"Periodically Swapping Modulation (P..." refers background in this paper

  • ...2714125 secondary side to reduce the circulating current [8]....

    [...]

Journal ArticleDOI
TL;DR: It is shown that TL converters are highly suitable for high input/output voltage and medium-to-high-power dc-dc power conversions and the virtues and drawbacks of these converters as compared to conventional converters.
Abstract: This paper discusses the basic family of three-level (TL) dc-dc converters. The origin of TL converters and their basic topological variations are described. Systematic procedures leading to improved and simplified circuit topologies are discussed. A feedforward control scheme that ensures the proper functioning of these converters is proposed. Moreover, the virtues and drawbacks of these converters as compared to conventional converters are highlighted. In particular, the advantages of TL converters include reduced voltage stress of the switches, reduced filter size, and improved dynamic response. It is shown that TL converters are highly suitable for high input/output voltage and medium-to-high-power dc-dc power conversions.

239 citations

Frequently Asked Questions (1)
Q1. What have the authors contributed in "Aalborg universitet periodically swapping modulation (psm) strategy for three-level (tl) dc/dc converters with balanced switch currents" ?

In this paper, a novel periodically swapping modulation ( PSM ) strategy is various types of TL DC/DC converters.