Photonic Networks-on-Chip for Future
Generations of Chip Multiprocessors
Assaf Shacham, Member, IEEE, Keren Bergman, Senior Member, IEEE,and
Luca P. Carloni, Member, IEEE
Abstract—The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power
that can be dissipated on a single die. We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intrachip and
off-chip communication on the overall power budget. The low loss properties of optical waveguides, combined with bit-rate
transparency, allow for a photonic interconnection network that can deliver considerably higher bandwidth and lower latencies with
significantly lower power dissipation than an interconnection network based only on electronic signaling. We explain why on-chip
photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize
its implementation. We introduce a novel hybrid microarchitecture for NoCs that combines a broadband photonic circuit-switched
network with an electronic overlay packet-switched control network. This design leverages the strength of each technology and
represents a flexible solution for the different types of messages that are exchanged on the chip; large messages are communicated
more efficiently through the photonic network, while short messages are delivered electronically with minimal power consumption. We
address the critical design issues including topology, routing algorithms, deadlock avoidance, and path-setup/teardown procedures.
We present experimental results obtained with
POINTS, an event-driven simulator specifically developed to analyze the proposed
design idea, as well as a comparative power analysis of a photonic versus an electronic NoC. Overall, these results confirm the unique
benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs.
Index Terms—On-chip communication, chip multiprocessors, photonics, emerging technologies.
Ç
1INTRODUCTION
I
N the continual drive toward improved microprocessor
performance, power efficiency has emerged as a prime
design consideration. In fact, the limitations on power
dissipation imposed by packaging constraints have become
so paramount that performance metrics are now typically
measured per unit power [1]. At the chip scale, the trend
toward multicore architectures and chip multiprocessors
(CMPs) for driving performance-per-watt by increasing the
number of parallel computational cores is dominating new
commercial releases [2], [3], [4], [5], [6]. With the future
path clearly toward further multiplication of the on-chip
processing cores, CMPs have begun to essentially resemble
highly parallel computing systems integrated on a single
chip. In this context, the role of the interconnect and
associated global communication infrastructure is becom-
ing central to the chip performance. As with highly parallel
systems, performance is increasingly tied to how efficiently
information is exchanged and how well the growing
number of computational resources are utilized. Thus,
global on-chip communications will play a central role in
the overall performance of future CMPs.
The realization of a scalable on-chip communication
infrastructure faces critical challenges in meeting the large
bandwidth capacities and stringent latency requirements
demanded by CMPs in a power-efficient fashion [7], [8].
Recent research on packet-switched networks-on-chip (NoC)
[9], [10], [11], [12] has shown that carefully engineered shared
links can provide enough bandwidth to replace many
traditional bus-based communication media and point-to-
point links. However, NoCs do not directly address the
power dissipation challenge. With vastly increasing on-chip
and off-chip communication bandwidths, the interconnect
power consumption is widely seen as an acutely growing
problem. It is unclear how electronic NoCs will continue to
satisfy future bandwidths and latency requirements within
the CMP power budget [13].
The insertion of photonics in the on-chip global inter-
connect structures for CMP can potentially leverage the
unique advantages of optical communication and capitalize
on the capacity, transparency, and fundamentally low
energy consumption that have made photonics ubiquitous
in long-haul transmission systems. The construction of
photonic NoC could deliver performance-per-watt scaling
that is simply not possible to reach with all-electronic
interconnects. The photonics opportunity is made possible
now by recent advances in nanoscale silicon photonics and
considerably improved photonic integration with commer-
cial CMOS chip manufacturing [14]. Unlike prior genera-
tions of photonic technologies, the remarkable capabilities
of nanoscale silicon photonics offer the possibility of
1246 IEEE TRANSACTIONS ON COMPUTERS, VOL. 57, NO. 9, SEPTEMBER 2008
. A. Shacham is with Aprius Inc., 440 N. Wolfe Rd., Sunnyvale, CA 94085.
E-mail: assaf@ee.columbia.edu.
. K. Bergman is with the Department of Electrical Engineering, Columbia
University, 500 W. 120th St., 1300 Mudd, New York, NY 10027.
E-mail: bergman@ee.columbia.edu.
. L.P. Carloni is with the Department of Computer Science, Columbia
University, 466 Computer Science Building, 1214 Amsterdam Avenue,
Mail Code: 0401, New York, NY 10027-7003.
E-mail: luca@cs.columbia.edu.
Manuscript received 5 July 2007; revised 3 Mar. 2008; accepted 13 Mar.
2008; published online 28 Apr. 2008.
Recommended for acceptance by R. Marculescu.
For information on obtaining reprints of this article, please send e-mail to:
tc@computer.org, and reference IEEECS Log Number TCSI-2007-07-0305.
Digital Object Identifier no. 10.1109/TC.2008.78.
0018-9340/08/$25.00 ß 2008 IEEE Published by the IEEE Computer Society
creating highly integrated photonic platforms for generat-
ing and receiving optical signals with fundamentally
superior power efficiencies. These tremendous gains in
power efficiencies for optical modulators and receivers are
driven by the nanoscale device footprints and correspond-
ing capacitances, as well as by the tight proximity of
electronic drivers enabled by the monolithic CMOS plat-
form integration [15], [16], [17], [18], [19]. Photonic elements
have recently become available as library cells in standard
CMOS processes. For the first time, we can practically
consider basing the communication infrastructure of a CMP
on a photonic interconnection network.
In particular, photonic NoCs can deliver a dramatic
reduction in power expended on intrachip global commu-
nications while satisfying the high bandwidths require-
ments of CMPs. Photonic NoCs change the rules of power
scaling: As a result of low loss optical waveguides, once a
photonic path is established, the data is transmitted end-to-
end without the need for repeating, regenerating, or
buffering. In electronic NoCs, on the other hand, a message
is buffered, regenerated, and then transmitted on the
interrouter links multiple times en route to its destination.
Furthermore, the switching and regenerating elements in
CMOS consume dynamic power that grows with the data
rate. The power consumption of optical switching elements,
conversely, is independent of the bit rate, so, once
generated, high-bandwidth messages do not consume
additional dynamic power when routed.
1
In this paper, we present photonic NoC as a solution for
high-performance CMP design which leverages the remark-
able progress in silicon photonics to offer a major reduction in
the power dissipated on intrachip communications. The
intrachip photonic infrastructure also offers seamless off-
chip communications. Specifically, we propose a hybrid NoC
microarchitecture that combines a photonic circuit-switched
network with an electronic packet-switched network. We
envision that, in the span of three or four CMOS process
generations, a similar photonic NoC will be implemented as
an additional layer of optical and optoelectronic devices
grownontopofthesilicondieandthemetallayers
comprising the CMP and possibly with multiple memory
planes in between. This will likely be realized using 3D
Integration (3DI) based on through-silicon via technology
[20] in order to separately optimize logic, memory, and Si
photonics planes. Further, current trends in multicore
architectures suggest that CMPs will soon host a few dozen
complex cores, each containing multiple logic blocks includ-
ing one or more processing units, a local memory, a direct
memory access (DMA) memory controller, and a network
interface. In our vision, the photonic NoC will be the global
communication medium connecting these cores among
themselves and with off-chip memories and devices.
1.1 Paper Organization and Contribution
Early versions of the work presented here were reported in
previous conference publications [21], [22], [23]. In this
paper, we collect the main results presented in these papers
and further extend the work with an improved power
dissipation estimation model and new performance simu-
lation results. This paper is organized as follows:
Section 2 briefly reviews prior work done by researchers
on the integration of optical communication elements in
electronic integrated circuits and, specifically, in micro-
processors. In Section 3, we give an overview of the hybrid
microarchitecture, we explain the rationale behind its
choice and we describe the most important photonic
components that characterize it. In Section 4, we discuss
in detail the critical design issues for the photonic NoC
including: technology building blocks, network topology,
routing algorithms, deadlock avoidance, and path-setup/
teardown procedures.
We developed
POINTS, an event-driven network traffic
simulator, to quantitatively evaluate critical design aspects
such as deadlock avoidance/recovery, optimal message
size, path multiplicity (PM), and alternative flow control
mechanisms. In Section 5, we report a series of simulation-
based experimental results that broadly confirm the
potential performance leap offered by the integration of a
photonic NoC in future high-performance CMPs. In
Section 6, we present a comparative power analysis of a
photonic NoC versus an electronic NoC that is designed to
provide the same bandwidth to the same number of cores.
The compelling conclusion of the study is that the power
expended on intrachip communications can be reduced by
nearly two orders of magnitude when high-bandwidth
communications is required among a large number of cores.
Last, we comment on future research avenues.
2RELATED WORK
Optical communication is widely accepted as an inter-
connection medium for long and medium-reach distances,
typically above 10 m [24]. A large body of research work
exists on the design, fabrication, and performance analysis
of optical interconnects for short-reach applications such as
chip-to-chip interconnection. Studies about intrachip appli-
cations for optical interconnects are not as widely available
because copper interconnects, until recently, have per-
formed sufficiently well in addressing intrachip commu-
nication needs within power constraints.
Collet et al. [25] have studied the relative performance of
optical and electrical on-chip interconnects for CMOS
processes between 0.7 and 0.05 m. They have concluded
that the penetration of on-chip optical interconnects can be
envisioned in lengths larger than 1,000 times the wave-
length (e.g., 45 m in a 45 nm process) where they can have
lower power and latency than electronic interconnects. The
work assumes the lasers are integrated into the silicon die
and are directly modulated, thus consuming the bulk of the
power of the optical system.
A multicore processor architecture where remote memory
accesses are implemented as transactions on a global on-chip
optical bus is suggested by Kirman etal. [26]. The work shows
a latency reduction as high as 50 percent for some applica-
tions and a power reduction of about 30 percent over a
baseline electrical bus. Because this design is based on bus
topology, it suffers from obvious scalability limits. The
simulated design connects 64 processing cores organized in
SHACHAM ET AL.: PHOTONIC NETWORKS-ON-CHIP FOR FUTURE GENERATIONS OF CHIP MULTIPRO CESSORS 1247
1. While this is true for the photonic network, the power consumption of
other network components (e.g., E/O and O/E conversion) does scale with
the bit rate, but it is still significantly lower than that of an electronic NoC.
A power analysis follows in Section 6.
four supernodes. It is expected that bus contention will limit
performance when a larger number of nodes are connected in
the bus. Additionally, optical buses are limited in the number
of terminals due to the finite launching power and coupling
losses incurred by each terminal.
An optical NoC based on a wavelength-routed crossbar is
presented by Brie
´
re et al. [27]. The crossbar, comprised of
passive resonator devices and routing between an input-
output pair, is achieved by selecting the appropriate
wavelength. This approach, however, requires either widely
tunable laser sources or large arrays of fixed-wavelength
sources with fast wavelength-selection switches. The perfor-
mance of such a system will strongly depend on the ability to
select a wavelength quickly and accurately and its scalability
will be limited by the number of fixed sources (or the tuning
range, if tunable lasers are used).
Intel’s Technology and Manufacturing Group performed
a study evaluating the benefits of optical intrachip inter-
connects [28]. Their conclusion is that, while optical clock
distribution networks are not especially attractive, wave-
length division multiplexing (WDM) does offer interesting
advantages for intrachip optical interconnects over copper
in deep-submicron processes.
Our work builds on these projects and suggests a system
where optical interconnects are used for intercore commu-
nication, thus replacing the global interconnects which are
generally long and stretch across the chip. The penetration
length is reduced by using on-chip modulators and simple
off-chip constant-wave laser sources [14]. The off-chip
lasers are cooled separately, thus dramatically reducing
the chip’s power and heat density. The topology used is of a
distributed network, which is scalable to a large number of
terminals. Current silicon technology is leveraged to design
a system which both consumes low power and is feasible
for fabrication in today’s or near-term silicon-photonic
technology.
3HYBRID NOCMICROARCHITECTURE
The photonic NoC microarchitecture employs a hybrid
design synergistically combining an optical circuit-
switched network for bulk message transmission and an
electronic packet-switched network for distributed control
and short message exchange. Hence, the term hybrid has a
twofold meaning: It denotes both the concept of combining
a circuit-switched network and a packet-switched network
as well as the idea of combining electronic and photonic
technologies.
While photonic technology offers unique advantages in
terms of energy and bandwidth, two necessary functions
for packet switching, namely, buffering and header proces-
sing, are very difficult to implement with optical devices.
On the other hand, electronic NoCs do have many
advantages in flexibility and abundant functionality, but
tend to consume high power, which scales up with the
transmitted bandwidth [29]. The hybrid approach that we
propose deals with this problem by employing two layers:
1. A photonic interconnection network, comprised of
silicon broadband photonic switches interconnected
by waveguides, is used to transmit large messages.
2. An electronic control network, topologically iden-
tical to the photonic network, is “folded” within the
photonic network to control its operations and
execute the exchange of short messages.
Every photonic message transmitted is preceded by an
electronic control packet (a path-setup packet) which is
routed in the electronic network, acquiring and setting up a
photonic path for the message. Buffering of messages is not
currently feasible in the photonic network as there are no
photonic equivalents for storage elements (e.g., flip-flops,
registers, RAM). Hence, buffering, if necessary, only takes
place for the electronic packets during the path-setup
phase. The photonic messages are transmitted without
buffering once the path has been acquired. This approach
can be seen as optical circuit switching: The established paths
are, in essence, optical circuits (or transparent lightpaths)
between processing cores, thus enabling low-power, low-
latency, high-bandwidth communications.
The main advantage of using photonic paths relies on a
property of the photonic medium, known as bit- rate
transparency [24]: Unlike routers based on CMOS technol-
ogy that must switch with every bit of the transmitted data,
leading to a dynamic power dissipation that scales with the
bit rate [29], photonic switches switch on and off once per
message and their energy dissipation does not depend on
the bit rate. This property facilitates the transmission of
very high-bandwidth messages while avoiding the power
cost that is typically associated with them in traditional
electronic networks.
Another attractive feature of optical communications
results from the low loss in optical waveguides: At the chip
scale, the power dissipated on a photonic link is completely
independent of the transmission distance. Energy dissipa-
tion remains essentially the same whether a message
travels between two cores that are 2 mm or 2 cm apart or
between two chips that are tens of centimeters apart—low
loss off-chip interconnects enable the seamless scaling of
the optical communication infrastructure to multichip
systems.
3.1 Exploiting Photonics in NoC Design
The proposed NoC is comprised of broadband 2 2 photonic
switching elements (PSEs) interconnected by optical wave-
guides. The PSEs can switch wavelength parallel messages
(i.e., each message is simultaneously encoded on several
wavelengths) as a single unit, with a subnanosecond switch-
ing time. The switches are arranged as a 2D matrix and
organized in groups of four. Each group is controlled by an
electronic circuit termed electronic router (ER) to construct a
4 4 switch. This structure lends itself conveniently to the
construction of planar 2D topologies such as a mesh or a
torus. A detailed explanation on the design of the PSEs and
the 4 4 switches is given in Section 4.
Two-dimensional topologies are the most suitable for the
construction of the proposed hybrid microarchitecture. The
same reasons that made them popular in electronic NoCs,
namely, their appropriateness for handling a large variety of
workloads and their good layout compatibility with a tiled
CMP chip [10], still apply in the photonic case. Further, large-
radix switches are very difficult to construct using PSEs, so
1248 IEEE TRANSACTIONS ON COMPUTERS, VOL. 57, NO. 9, SEPTEMBER 2008
the low-radix switches, the building blocks of mesh/torus
networks, are a better fit. A key advantage of photonic
implementations of meshes and tori is related to the nature of
the guided waves. When two waveguides intersect at a right
angle, as they do many times in mesh and torus networks, the
waves continue propagating in their original direction and
the crosstalk is negligible. This property enables the con-
struction of the photonic NoC in a single layer, above the metal
stack, thus reducing the fabrication complexity, the chip
dimensions, and the total cost.
Torus networks offer a lower network diameter com-
pared to meshes, at the expense of having longer links [30].
Hence, they are a better choice for photonic NoCs since the
transmission power on photonic links is independent of the
length, unlike in copper lines. Topology can also be
employed to address issues caused by the lack of buffering
in photonics. Since the PSEs have small area and power
consumption, many of them can be used to provision the
network with additional paths on which circuits can be
created, thus reducing the contention manifested as path-
setup latency.
Electronic/Optical and Optical/Electronic (E/O and O/
E) conversions are necessary for the exchange of photonic
messages on the NoC. Each core in the CMP, therefore,
includes a network gateway serving as a photonic network
interface. Small footprint microring-resonator-based sili-
con optical modulators with data rates up to 12.5 Gbps
[31] as well as 10 Gbps Mach-Zehnder silicon modulators
[14], [16] and SiGe photodetectors [32] have been
reported and have recently become commercially avail-
able [14] for photonic chip-to-chip interconnect systems
(see Fig. 1). The laser sources, as in many off-chip optical
communication systems [14], can be located off chip and
coupled into the chip using optical fibers or, alternatively,
can be bonded to the silicon die, constructing hybrid-
evanescent laser sources [33].
The network gateways also include some circuitry for
clock synchronization and recovery and serialization/
deserialization. When traditional approaches are used, this
circuitry can be expensive both in terms of power and of
latency. New technological opportunities enabled by the
integration of photonics onto the silicon die may reduce
these costs. An example of such an opportunity is an optical
clock distribution network which can provide a high-
quality low-power clock to the entire chip, simplifying the
clock recovery in the gateways.
Since electronic signals are fundamentally limited in
their bandwidth to a few gigahertz, larger data capacity is
typically obtained by increasing the number of parallel
wires. The optical equivalent of this wire parallelism can be
provided by a large number of simultaneously modulated
wavelengths using WDM [34] at the network interfaces.
The translating device, which can be implemented using
microring resonator modulators, converts directly between
space-parallel electronics and wavelength-parallel photo-
nics in a manner that conserves chip space as the translator
scales to very large data capacities [35], [36]. The energy
dissipated in these large parallel structures is not small, but
it is still smaller then the energy consumed by the wide
buses and buffers currently used in NoCs. The network
gateway interface and corresponding E/O and O/E
conversions occur once per core in the proposed system,
compared to multiple ports at each router in electronic
equivalent NoCs. A study of the power dissipated by the
proposed hybrid NoC and a comparison with an all-
electronic NoC architecture is given in Section 6.
3.2 Life of a Message in the Photonic NoC
To illustrate the operation of the proposed NoC, we
describe the typical chain of events in the transmission of
a message between two ports placed on different cores in
the CMP, for example, a write operation that takes place
from a processing unit in a core to a memory that is located
in another core. As soon as the write address is known,
possibly even before the contents of the message are ready,
a path-setup packet is sent on the electronic control network.
The packet includes destination address information and,
perhaps, additional control information such as priority or
flow ID. The control packet is routed in the electronic
network, reserving the photonic switches along the path for
the photonic message which will follow it. At every router
in the path, a next-hop decision is made according to the
routing algorithm used in the network.
When the path-setup packet reaches the destination port,
the photonic path is reserved and is ready to route the
message. Since the photonic path is completely bidirec-
tional, a short light pulse can then be transmitted onto the
waveguide in the opposite direction (from the destination
to the source), signaling to the source that the path is open.
This technique is similar to the one described in detail by
Shacham and Bergman in [37]. When the optical pulse is
received at the message source, the optical link is
established. The photonic message transmission then
begins and the message follows the path from switch to
switch until it reaches its destination.
After the message transmission is completed, a path-
teardown packet is sent to free the path resources for usage
by other messages. Once the photonic message has been
received and checked for errors, a small acknowledgment
packet may be sent on the electronic control network to
support guaranteed-delivery protocols.
In the case where a path-setup packet is dropped in the
router due to congestion, a path-blocked packet is transmitted
SHACHAM ET AL.: PHOTONIC NETWORKS-ON-CHIP FOR FUTURE GENERATIONS OF CHIP MULTIPRO CESSORS 1249
Fig. 1. Building blocks examples. (a) A silicon nanophotonic wavelength-
insensitive switch [19]. (b) An ultracompact 10 Gbps silicon modulator
[16]. (c) CMOS-compatible waveguides and holographic fiber-coupling
lens for off-chip access [14].
by the dropping router to the source, backtracking the
path traveled by the path-setup packet. The path-blocked
packet releases the reserved switches and notifies the core
attempting transmission that its request was not served.
The source may then attempt transmission again and take
advantage of PM in the network.
4NETWORK DESIGN
The design of the photonic NoC requires an approach
fundamentally different, in many aspects, from electronic
NoCs. In this section, we describe in detail the proposed
implementation, including the network’s electronic and
photonic building blocks, topology, routing algorithms,
and flow control.
4.1 Building Blocks
The main building block of the photonic NoC is a broadband
PSE, based on a microring-resonator structure. A similar
device, although optically pumped, was recently reported in
[19]. The switch is, in essence, a waveguide intersection,
positioned between two ring-shaped waveguide structures
(i.e., microring resonators). The rings have a certain
resonance frequency, derived from material and structural
properties. The PSE can be in one of two possible states:
. OFF state: The resonant frequency of the rings is
different from the wavelength (or wavelengths) on
which the optical data stream is modulated. Hence,
the light passes through the waveguide intersection
uninterrupted, as if it is a passive waveguide
crossover (Fig. 2a).
. ON state: The switch is turned on by the injection of
electrical current into p-n contacts surrounding the
rings; the resonance of the rings shifts so that the
light, now on resonance, is coupled into the rings,
making a right angle turn, thus causing a switching
action (Fig. 2b).
Photonic switching elements and modulators based on
these effects have been realized in silicon and a switching
time of 30 ps has been experimentally demonstrated [31].
Their merit lies mainly in their extremely small footprint,
with ring diameters of approximately 12 m , and their low
power consumption of less than 0.5 mW of DC power
when ON and approximately 1 pJ for modulating narrow-
band single-wavelength signals. For switching multiwave-
length broadband signals, the ring resonators are designed
as comb-pass filters with somewhat larger footprints,
consuming 10 mW when ON [15], [18]. When the switches
are OFF, they act as passive devices consuming nearly no
power. Ring-resonator-based switches exhibit good cross-
talk properties (> 20 dB), and a low insertion loss,
approximately 1.5 dB [38].
Recent results reported in [19] (see Fig. 1a) demonstrate
an optically pumped PSE with a measured insertion loss of
2.5 dB in the pass-band, capable of simultaneously switch-
ing nine 40 Gbps wavelengths. The switch is compact ð40
12mÞ and has a switching time < 2 ns. It is reasonable to
assume that the loss figures can be improved with
advances in fabrication techniques and that electrically
pumped devices, necessary to enable fabrication and
electronic control will be developed.
The PSEs are interconnected by silicon waveguides,
carrying the photonic signals, and are organized in groups
of four. Each quadruplet, controlled by an electronic circuit
termed an ER, forms a 4 4 switch (Fig. 3). The 4 4 switches
are therefore interconnected by the inter-PSE waveguides
and by the metal lines connecting the ERs. Control packets
(e.g., path-setup) are received in the ER, processed, and sent
to their next hop, while the PSEs are switched ON and OFF
accordingly. Once a packet completes its journey through a
sequence of ERs, a chain of PSEs is ready to route the optical
message. Owing to the small footprint of the PSEs and the
simplicity of the ER, which only processes small control
packets, the 4 4 switch can have a very small area. Based on
the size of the microring resonator devices [19], [31] and the
minimal logic required to implement the ER, this area is
estimated to be about 70 70m.
A keen observer will notice that the 4 4 switch in Fig. 3
is blocking. For example, a message routed from South to
East will block message requests from West to South and
from East to North. In general, every message that makes a
wide turn (i.e., a turn involving three PSEs) may block two
other message requests that attempt to make wide turns.
Messages that make narrow turns (e.g., South to West) and
messages that are routed straight through do not block
other messages and cannot be blocked. To limit the
blocking problem, U-turns within the switches are for-
bidden. The blocking relationships between messages are
summarized in Table 1.
It is an important requirement for an atomic switch to
have a nonblocking property in an interconnection net-
work. Nonblocking switches offer improved performance
and simplify network management and routing. However,
constructing a nonblocking 4 4 switch with the given
photonic building blocks requires an exceedingly complex
structure. This has a negative impact on the area and,
more importantly, the optical signal integrity, as each PSE
hop introduces additional loss and crosstalk. The design
choice is, therefore, to use the blocking switch because of
1250 IEEE TRANSACTIONS ON COMPUTERS, VOL. 57, NO. 9, SEPTEMBER 2008
Fig. 2. PSE: (a) OFF state: A passive waveguide crossover. (b) ON
state: Light is coupled into rings and forced to turn.
Fig. 3. A 4 4 switch. Four PSE controlled by an electronic router (ER).
