Journal ArticleDOI
Physical Insight Toward Heat Transport and an Improved Electrothermal Modeling Framework for FinFET Architectures
Mayank Shrivastava,M. Agrawal,S. Mahajan,Harald Gossner,T. Schulz,Dinesh K. Sharma,Valipe Ramgopal Rao +6 more
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TLDR
In this article, a detailed physical insight on the lattice heating and heat flux in a 3D front end of the line and complex back end of line of a logic circuit network is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD.Abstract:
We report on the thermal failure of fin-shaped field-effect transistor (FinFET) devices under the normal operating condition. Pre- and post failure characteristics are investigated. A detailed physical insight on the lattice heating and heat flux in a 3-D front end of the line and complex back end of line-of a logic circuit network-is given for bulk/silicon-on-insulator (SOI) FinFET and extremely thin SOI devices using 3-D TCAD. Moreover, the self-heating behavior of both the planar and nonplanar devices is compared. Even bulk FinFET shows critical self-heating. Layout, device, and technology design guidelines (based on complex 3-D TCAD) are given for a robust on-chip thermal management. Finally, an improved framework is proposed for an accurate electrothermal modeling of various FinFET device architectures by taking into account all major heat flux paths.read more
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Proceedings ArticleDOI
Self-heat reliability considerations on Intel's 22nm Tri-Gate technology
Chetan Prasad,Lei Jiang,Dhruv Singh,M. Agostinelli,C. Auth,P. Bai,Travis Eiles,J. Hicks,Chia-Hong Jan,Kaizad Mistry,Sanjay Natarajan,B. Niu,Paul A. Packan,Daniel Pantuso,Ian R. Post,S. Ramey,A. Schmitz,Sell Bernhard,S. Suthram,J. Thomas,Curtis Tsai,P. Vandervoorn +21 more
TL;DR: In this article, the authors describe various measurements on self-heat performed on Intel's 22nm process technology and outline its reliability implications, comparing them to thermal modeling results and analytical data.
Journal ArticleDOI
Analytical Thermal Model for Self-Heating in Advanced FinFET Devices With Implications for Design and Reliability
TL;DR: A rigorous analytical thermal model has been formulated for the analysis of self-heating effects in FinFETs, under both steady-state and transient stress conditions, which is critical for improving circuit performance and electrical overstress/electrostatic discharge (ESD) reliability.
Journal ArticleDOI
A Thermal-Aware Device Design Considerations for Nanoscale SOI and Bulk FinFETs
TL;DR: In this article, the thermal performance characteristics of fin-shaped FETs (FinFETs) are studied and analyzed for sub-22-nm technologies using the well-calibrated TCAD simulations.
Journal ArticleDOI
3D Modeling of Spatio-temporal Heat-transport in III-V Gate-all-around Transistors Allows Accurate Estimation and Optimization of Nanowire Temperature
TL;DR: In this article, a 3D electrothermal simulation model is developed to explore and interpret self-heating and heat dissipation in gate-all-around (GAA) devices.
Posted Content
Freely scalable and reconfigurable optical hardware for deep learning
TL;DR: A digital optical neural network (DONN) with intralayer optical interconnects and reconfigurable input values with path-length-independence of optical energy consumption is proposed and it is found that digital optical data transfer is beneficial over electronics when the spacing of computational units is on the order of $$>10\,\upmu $$ > 10 μ m.
References
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Book
FinFETs and Other Multi-Gate Transistors
TL;DR: FinFETs and Other Multi-Gate Transistors provides a comprehensive description of the physics, technology and circuit applications of multigate field-effect transistors (FET) and explains the physics and properties.
Journal ArticleDOI
Measurement and modeling of self-heating in SOI nMOSFET's
TL;DR: In this article, the authors measured and modeled self-heating in SOI nMOSFETs under static operating conditions and showed that the measured temperature rise agrees well with the predictions of an analytical model and is a function of the silicon thickness, buried oxide thickness, and channel-metal contact separation.
Proceedings ArticleDOI
High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding
Olivier Weber,O. Faynot,Francois Andrieu,C. Buj-Dufournet,F. Allain,P. Scheiblin,J. Foucher,Nicolas Daval,D. Lafond,L. Tosti,L. Brevard,Olivier Rozeau,Claire Fenouillet-Beranger,M. Marin,Frederic Boeuf,Daniel Delprat,Konstantin Bourdelle,Bich-Yen Nguyen,Simon Deleonibus +18 more
TL;DR: In this paper, the authors investigated the sources responsible for local and inter-die threshold voltage variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack.
Journal ArticleDOI
Low-Resistance Electrical Contact to Carbon Nanotubes With Graphitic Interfacial Layer
Yang Chai,Arash Hazeghi,Kuniharu Takei,Hong-Yu Chen,Philip C. H. Chan,Ali Javey,Hon-Sum Philip Wong +6 more
TL;DR: In this paper, a graphitic interfacial layer catalyzed by a Ni layer was used to improve the electrical contact between carbon nanotubes and metal, and the capping metal and Ni catalyst were selectively removed and replaced with new metal pads without further annealing.
Journal ArticleDOI
Thermal conduction in silicon micro- and nanostructures
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