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Journal ArticleDOI

Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks

TL;DR: A methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures is presented and a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonics network are described.
Abstract: Photonic technology is becoming an increasingly attractive solution to the problems facing today's electronic chip-scale interconnection networks. Recent progress in silicon photonics research has enabled the demonstration of all the necessary optical building blocks for creating extremely high-bandwidth density and energy-efficient links for on-chip and off-chip communications. From the feasibility and architecture perspective however, photonics represents a dramatic paradigm shift from traditional electronic network designs due to fundamental differences in how electronics and photonics function and behave. As a result of these differences, new modeling and analysis methods must be employed in order to properly realize a functional photonic chip-scale interconnect design. In this paper, we present a methodology for characterizing and modeling fundamental photonic building blocks which can subsequently be combined to form full photonic network architectures. We also describe a set of tools which can be utilized to assess the physical-layer and system-level performance properties of a photonic network. The models and tools are integrated in a novel open-source design and simulation environment. We present a case study of two different photonic networks-on-chip to demonstrate how our improved understanding and modeling of the physical-layer details of photonic communications can be used to better understand the system-level performance impact.

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Citations
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Journal ArticleDOI
TL;DR: A co-design approach for building silicon photonic interconnection networks that leverages the unique optical data movement capabilities and offers a path toward realizing future Exascale systems is presented.
Abstract: With the extraordinary growth in parallelism at all system scales driven by multicore architectures, computing performance is increasingly determined by how efficiently high-bandwidth data is communicated among the numerous compute resources. High-performance systems are especially challenged by the growing energy costs dominated by data movement. As future computing systems aim to realize the Exascale regime—surpassing 1018 operations per second—achieving energy efficient high-bandwidth communication becomes paramount to scaled performance. Silicon photonics offers the possibility of delivering the needed communication bandwidths to match the growing computing powers of these highly parallel architectures with extremely scalable energy efficiency. However, the insertion of photonic interconnects is not a one-for-one replacement. The lack of practical buffering and the fundamental circuit switched nature of optical data communications require a holistic approach to designing system-wide photonic interconnection networks. New network architectures are required and must include arbitration strategies that incorporate the characteristics of the optical physical layer. This paper reviews the recent progresses in silicon photonic based interconnect devices along with the system level requirements for Exascale. We present a co-design approach for building silicon photonic interconnection networks that leverages the unique optical data movement capabilities and offers a path toward realizing future Exascale systems.

128 citations

Journal ArticleDOI
TL;DR: In the worst case, the crosstalk noise power exceeds the signal power in all three WDM-based ONoC architectures, even when the number of processor cores is small, e.g., 64.
Abstract: Optical networks-on-chip (ONoCs) using wavelength-division multiplexing (WDM) technology have progressively attracted more and more attention for their use in tackling the high-power consumption and low bandwidth issues in growing metallic interconnection networks in multiprocessor systems-on-chip. However, the basic optical devices employed to construct WDM-based ONoCs are imperfect and suffer from inevitable power loss and crosstalk noise. Furthermore, when employing WDM, optical signals of various wavelengths can interfere with each other through different optical switching elements within the network, creating crosstalk noise. As a result, the crosstalk noise in large-scale WDM-based ONoCs accumulates and causes severe performance degradation, restricts the network scalability, and considerably attenuates the signal-to-noise ratio (SNR). In this paper, we systematically study and compare the worst case as well as the average crosstalk noise and SNR in three well-known optical interconnect architectures, mesh-based, folded-torus-based, and fat-tree-based ONoCs using WDM. The analytical models for the worst case and the average crosstalk noise and SNR in the different architectures are presented. Furthermore, the proposed analytical models are integrated into a newly developed crosstalk noise and loss analysis platform (CLAP) to analyze the crosstalk noise and SNR in WDM-based ONoCs of any network size using an arbitrary optical router. Utilizing CLAP, we compare the worst case as well as the average crosstalk noise and SNR in different WDM-based ONoC architectures. Furthermore, we indicate how the SNR changes in respect to variations in the number of optical wavelengths in use, the free-spectral range, and the microresonators $\boldsymbol {Q}$ factor. The analyses’ results demonstrate that the crosstalk noise is of critical concern to WDM-based ONoCs: in the worst case, the crosstalk noise power exceeds the signal power in all three WDM-based ONoC architectures, even when the number of processor cores is small, e.g., 64.

75 citations


Additional excerpts

  • ...The fundamental limits for the number of WDM channels and power per channel when using building blocks that include silicon waveguides, silicon microring modulators, and filters were described in [17]....

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  • ...Chan et al. [14] proposed a methodology to characterize and model basic photonic blocks, which can form full photonic network architectures, and used a physical-layer simulator to assess the physical-layer and system-level performance of a photonic network....

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Journal ArticleDOI
TL;DR: It is found that crosstalk noise can significantly limit the scalability of mesh-based ONoCs, and it is shown that symmetric meshes have the best SNR performance.
Abstract: Crosstalk noise is an intrinsic characteristic as well as a potential issue of photonic devices. In large scale optical networks-on-chips (ONoCs), crosstalk noise could cause severe performance degradation and prevent ONoC from communicating properly. The novel contribution of this paper is the systematical modeling and analysis of the crosstalk noise and the signal-to-noise ratio (SNR) of optical routers and mesh-based ONoCs using a formal method. Formal analytical models for the worst-case crosstalk noise and minimum SNR in mesh-based ONoCs are presented. The crosstalk analysis is performed at device, router, and network levels. A general 5 × 5 optical router model is proposed for router level analysis. The minimum SNR optical link candidates, which constrain the scalability of mesh-based ONoCs, are identified. It is also shown that symmetric mesh-based ONoCs have the best SNR performance. The presented formal analyses can be easily applied to other optical routers and mesh-based ONoCs. Finally, we present case studies of mesh-based ONoCs using the optimized crossbar and Crux optical routers to evaluate the proposed formal method. We find that crosstalk noise can significantly limit the scalability of mesh-based ONoCs. For example, when the mesh-based ONoC size, using optimized crossbar, is larger than 8 × 8, the optical signal power is smaller than the crosstalk noise power; when the network size is 16 × 16 and the input power is 0 dBm, in the worst-case, the signal power is -24.9 dBm and the crosstalk noise power is -11 dBm.

72 citations


Additional excerpts

  • ...D IC technologies....

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Journal ArticleDOI
TL;DR: For the first time, this paper systematically analyzes and models the worst-case crosstalk noise and SNR in folded-torus-based ONoCs and presents a novel cros stalks noise and loss analysis platform, called CLAP, which can analyze the crosStalk noiseand SNR of arbitrary O noCs.
Abstract: Photonic devices are widely used in optical networks-on-chip (ONoCs) and suffer from crosstalk noise. The accumulative crosstalk noise in large scale ONoCs diminishes the signal-to-noise ratio (SNR), causes severe performance degradation, and constrains the network scalability. For the first time, this paper systematically analyzes and models the worst-case crosstalk noise and SNR in folded-torus-based ONoCs. Formal analytical models for the worst-case crosstalk noise and SNR are presented. The crosstalk noise analysis is hierarchically performed at the basic photonic device level, then at the optical router level, and finally at the network level. We consider a general 5 × 5 optical router model to enable crosstalk noise and SNR analyses in folded-torus-based ONoCs using an arbitrary 5 × 5 optical router. Using the general optical router model, the worst-case SNR link candidates, which restrict the network scalability, are found. Also, we present a novel crosstalk noise and loss analysis platform, called CLAP, which can analyze the crosstalk noise and SNR of arbitrary ONoCs. Case studies of optimized crossbar and Crux optical routers using recent photonic device parameters are presented. Moreover, we compare the worst-case crosstalk noise and SNR in folded-torus-based and mesh-based ONoCs using optimized crossbar and Crux optical routers. The quantitative simulation results show the critical behavior of crosstalk noise in large scale ONoCs. For example, in folded-torus-based ONoCs using the Crux optical router, the noise power exceeds the signal power for network sizes larger than 12 × 12; when the network size is 20 × 20 and the injection signal power equals 0 dBm, the signal power and noise power are -9.4 dBm and -6.1 dBm, respectively.

59 citations


Cites methods from "Physical-Layer Modeling and System-..."

  • ...Using the abstract router region, the waveguide crossings and bendings at the network level are integrated into the router level model....

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Journal ArticleDOI
TL;DR: This work improves upon the circuit-switching paradigm by introducing the use of on-chip wavelength-selective spatial routing to produce multiple logical communication layers on a single physical plane, which yields higher path diversity in photonic interconnection networks.
Abstract: The overall performance of modern computing systems is increasingly determined by the characteristics of the interconnection network used to provide communication links between on-chip cores and off-chip memory. Photonic technology has been proposed as an alternative to traditional electronic interconnects because of its advantages in bandwidth density, latency, and power efficiency. Circuit-switched photonic interconnect topologies take advantage of the optical spectrum to create high-bandwidth transmission links through the transmission of data channels on multiple parallel wavelengths; however, this technique suffers from low path diversity and high setup time overhead, which induces high network resource contention, unfairness, and long latencies. This work improves upon the circuit-switching paradigm by introducing the use of on-chip wavelength-selective spatial routing to produce multiple logical communication layers on a single physical plane. This technique yields higher path diversity in photonic interconnection networks, demonstrating as much as 764% saturation bandwidth improvement with synthetic traffic and as much as 89% improvement in execution time and energy dissipation for traffic from scientific application traces.

58 citations

References
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Journal ArticleDOI
10 Jun 2009
TL;DR: The current performance and future demands of interconnects to and on silicon chips are examined and the requirements for optoelectronic and optical devices are project if optics is to solve the major problems of interConnects for future high-performance silicon chips.
Abstract: We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

1,959 citations


"Physical-Layer Modeling and System-..." refers background in this paper

  • ...The views, opinions, and findings contained in this paper are those of the authors and should not be interpreted as representing the official views or policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the Department of Defense....

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  • ...The device characteristics can be determined experimentally, through simulation, or projected....

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Journal ArticleDOI
TL;DR: In this paper, the trade-offs between resonantly enhanced group delay, device size, insertion loss and operational bandwidth are analyzed for various delay-line designs, and a large fractional group delay exceeding 10 bits is achieved for bit rates as high as 20 Gbps.
Abstract: On-chip optical buffers based on waveguide delay lines might have significant implications for the development of optical interconnects in computer systems. Silicon-on-insulator (SOI) submicrometre photonic wire waveguides are used, because they can provide strong light confinement at the diffraction limit, allowing dramatic scaling of device size. Here we report on-chip optical delay lines based on such waveguides that consist of up to 100 microring resonators cascaded in either coupled-resonator or all-pass filter (APF) configurations. On-chip group delays exceeding 500 ps are demonstrated in a device with a footprint below 0.09 mm2. The trade-offs between resonantly enhanced group delay, device size, insertion loss and operational bandwidth are analysed for various delay-line designs. A large fractional group delay exceeding 10 bits is achieved for bit rates as high as 20 Gbps. Measurements of system-level metrics as bit error rates for different bit rates demonstrate error-free operation up to 5 Gbps.

1,161 citations


"Physical-Layer Modeling and System-..." refers background in this paper

  • ...The ports of the device are enumerated 0. . ....

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Journal ArticleDOI
TL;DR: It is shown that the micrometer-long silicon-on-insulator-based nanotaper coupler is able to efficiently convert both the mode field profile and the effective index, with a total length as short as 40 microm, during compact mode conversion between a fiber and a submicrometer waveguide.
Abstract: We propose and demonstrate an efficient coupler for compact mode conversion between a fiber and a submicrometer waveguide. The coupler is composed of high-index-contrast materials and is based on a short taper with a nanometer-sized tip. We show that the micrometer-long silicon-on-insulator-based nanotaper coupler is able to efficiently convert both the mode field profile and the effective index, with a total length as short as 40 microm. We measure an enhancement of the coupling efficiency between an optical fiber and a waveguide by 1 order of magnitude due to the coupler.

994 citations


"Physical-Layer Modeling and System-..." refers background in this paper

  • ...Lateral coupling can be accomplished by building a nanotaper at the perimeter of a chip to couple into a fiber and has been calculated to have theoretical losses of under 1 dB [31]....

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Journal ArticleDOI
TL;DR: A scheme for achieving high-speed operation for carrier-injection based silicon electro-optical modulator, which is optimized for small size and high modulation depth is shown.
Abstract: We show a scheme for achieving high-speed operation for carrier-injection based silicon electro-optical modulator, which is optimized for small size and high modulation depth. The performance of the device is analyzed theoretically and a 12.5-Gbit/s modulation with high extinction ratio >9dB is demonstrated experimentally using a silicon micro-ring modulator.

930 citations


"Physical-Layer Modeling and System-..." refers background in this paper

  • ...5 Gb/s in a 5-μm radius silicon ring resonator [36]....

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Journal ArticleDOI
TL;DR: Results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs, as well as a comparative power analysis of a photonic versus an electronic NoC.
Abstract: The design and performance of next-generation chip multiprocessors (CMPs) will be bound by the limited amount of power that can be dissipated on a single die We present photonic networks-on-chip (NoC) as a solution to reduce the impact of intra-chip and off-chip communication on the overall power budget A photonic interconnection network can deliver higher bandwidth and lower latencies with significantly lower power dissipation We explain why on-chip photonic communication has recently become a feasible opportunity and explore the challenges that need to be addressed to realize its implementation We introduce a novel hybrid micro-architecture for NoCs combining a broadband photonic circuit-switched network with an electronic overlay packet-switched control network We address the critical design issues including: topology, routing algorithms, deadlock avoidance, and path-setup/tear-down procedures We present experimental results obtained with POINTS, an event-driven simulator specifically developed to analyze the proposed idea, as well as a comparative power analysis of a photonic versus an electronic NoC Overall, these results confirm the unique benefits for future generations of CMPs that can be achieved by bringing optics into the chip in the form of photonic NoCs

873 citations


"Physical-Layer Modeling and System-..." refers background in this paper

  • ...With link-level simulation, the primary concern is detailed physical modeling of all the end-to-end aspects of a photonic path to determine performance metrics such as signal integrity and link reliability....

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