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Proceedings ArticleDOI

Physical mechanisms of short-channel effects of lateral double-gate tunnel FET

29 Jun 2017-pp 34-35

AbstractThis paper discusses the mechanisms that may underlie the short-channel effects of the lateral double-gate tunnel FET. Simulations suggest that the short-channel effect of the threshold voltage is triggered by degradation in the electrostatic integrity of the gate field.

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Citations
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Journal ArticleDOI
Abstract: Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate–drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.

15 citations


Cites background from "Physical mechanisms of short-channe..."

  • ...The gate length Lg is set as 100 nm to exclude the short-channel effect of threshold voltage [24], [25]....

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References
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Journal ArticleDOI
Abstract: A formula is derived, which shows that the subthreshold swing of field-effect interband tunnel transistors is not limited to 60 mV/dec as in the MOSFET. This formula is consistent with two recent reports of interband tunnel transistors, which show lower than 60-mV/dec subthreshold swings and provides two simple design principles for configuring these transistors. One of these principles suggests placing the gate adjacent to the tunnel junction. Modeling of this configuration verifies that sub-60-mV/dec swing is possible.

523 citations

Journal ArticleDOI
Abstract: Low operating power is an important concern for sub-45-nm CMOS integrated circuits. Scaling of devices to below 45 nm leads to an increase in active power dissipation (CV2.f) and subthreshold power (IOFF.VDD)Hence, new device innovations are being explored to address these problems. In this paper, we simulate and experimentally investigate the source-pocket tunnel field-effect transistor (TFET), which is based on the principle of band-to-band tunneling, p-i-n and source-pocket TFETs are fabricated with different pocket conditions to observe the effect of the source-side pocket on device performance. Different annealing schemes (spike and conventional rapid thermal annealing) are used to study the effect of annealing conditions on TFET performance. The source-pocket TFET shows a higher ION (~10 times) and steeper subthreshold swing as compared to a p-i-n TFET. The ambipolar conduction is also reduced by using a low-doped drain extension. Low-temperature measurements of the source-pocket TFET were performed, and the subthreshold swing of the source-pocket TFET shows very little temperature dependence, which confirms the dominant source injection mechanism to be band-to-band tunneling.

194 citations

Journal ArticleDOI
Abstract: We report on a lateral interband tunneling transistor, where the source and drain form a heavily doped lateral pn junction in a thin Si film on a silicon-on-insulator (SOI) substrate. The transistor action results from the control of the reverse-bias tunneling breakdown under drain bias VD by a gate voltage VG. We observe gate control over tunneling drain current ID at both polarities of VG with negligible gate leakage. Systematic ID(VG,VD) measurements, together with numerical device simulations, show that in first approximation ID depends on the maximum junction electric field Fmax(VG,VD). Excellent performance is hence predicted in devices with more abrupt junctions and thinner SOI films. The device does not have an inversion channel and is not subject to scaling rules of standard Si transistors.

142 citations

Journal ArticleDOI
Abstract: This work reports on the physical definition and extraction of threshold voltage in Tunnel FETs (field effect transistors) based on numerical simulation data. It is shown that the Tunnel FET has the outstanding property of having two threshold voltages: one in terms of gate voltage, VTG, and one in terms of drain voltage, VTD. These threshold voltages can be physically defined based on the transition between a quasi-exponential dependence, and a linear dependence of the drain current on VGS or VDS, and by extension, on the saturation of the tunneling energy barrier width narrowing. The extractions of VTG and VTD are performed based on the transconductance change method in the double gate Tunnel FET with a high-k dielectric, and a systematic comparison with the constant current method is reported. The effect of gate length scaling on these Tunnel FETs' threshold voltages, as well as the dependence of VTG on applied drain voltage and VTD on applied gate voltage, are investigated.

122 citations

Journal ArticleDOI
Abstract: An analytical charge model for double gate (DG) tunnel FETs (TFETs) is proposed. By splitting the TFET into a series combination of a gated tunnel diode and a DG MOSFET, we solved the Poisson equation with matching boundary conditions to obtain a surface potential model for the DG TFET. Based on that, the source depletion charge and the mobile channel charge are derived. Comparisons between the proposed model and TCAD simulations show good agreements and suggest a 100/0 drain/source channel inversion charge partition. Terminal capacitances calculated based on the proposed charge model are also evaluated and show good agreement with TCAD simulations.

86 citations