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Proceedings ArticleDOI

Physical mechanisms of short-channel effects of lateral double-gate tunnel FET

TL;DR: In this article, the authors discuss the mechanisms that may underlie the short-channel effects of the lateral double-gate tunnel FET and suggest that the short channel effect of the threshold voltage is triggered by degradation in the electrostatic integrity of the gate field.
Abstract: This paper discusses the mechanisms that may underlie the short-channel effects of the lateral double-gate tunnel FET. Simulations suggest that the short-channel effect of the threshold voltage is triggered by degradation in the electrostatic integrity of the gate field.
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Journal ArticleDOI
TL;DR: Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field effect transistors (TFETs) is developed in this article.
Abstract: Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate–drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.

22 citations


Cites background from "Physical mechanisms of short-channe..."

  • ...The gate length Lg is set as 100 nm to exclude the short-channel effect of threshold voltage [24], [25]....

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Posted ContentDOI
07 Jun 2023
TL;DR: In this paper , an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET) is proposed.
Abstract: Abstract In this paper, we propose a inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium layer is introduced on the source side to form a heterojunction, effectively improving the device's conduction current. An ETL is incorporated to combat tunneling leakage, resulting in a steeper subthreshold swing. Furthermore, a CEI consisting of Si 3 N 4 is introduced between the germanium source and the Schottky metal, which effectively reduces carrier losses in the inversion layer and improves the overall device performance. This study presents a calibration-based approach to simulations, taking into account practical process considerations. Simulation results show that at V D = 0.2 V, the CEI ETL GS-iTFET achieves an average subthreshold swing ( SS avg ) of 30.5 mV/dec, an I on of 3.12x10 -5 A/μm and an I on / I off ratio of 1.81x10 10 . These results demonstrate a significantly low subthreshold swing and a high current ratio of about 10 10 . In addition, the proposed device eliminates the need for multiple implantation processes, resulting in significant manufacturing cost reductions. As a result, the CEI ETL GS-iTFET shows remarkable potential in future low-power device competition.
References
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Journal ArticleDOI
TL;DR: In this article, two possible extrapolation-type methods to extract the threshold voltage of tunnel field effect transistors (TFETs) are proposed, which are based on defining threshold voltage as the gate voltage axis intercept of the linearly extrapolated strong conduction behavior of either CRT or H 1 functions.
Abstract: This article proposes two possible extrapolation-type methods to extract the threshold voltage of Tunnel Field Effect Transistors (TFETs). The first one, which we call the “ CTR method,” makes use of the drain Current-to-Transconductance Ratio function. As this method requires differentiating the drain current with respect to the gate voltage, it is blurred by the amplified effect of measurement noise when applied to real device transfer characteristics. To avoid this effect, a second method is also proposed that uses integration of the drain current with respect to gate voltage instead of differentiation. This second method, which was named “ H 1 method” when it was originally applied to non-crystalline inversion mode MOSFETs, produces comparable results to those obtained from the CTR method, but it has the advantage of inherently reducing the effect of measurement noise by virtue of the low-pass filtering capacity of integration. Both methods are based on defining threshold voltage as the gate voltage axis intercept of the linearly extrapolated strong conduction behavior of either CRT or H 1 functions. This is made possible by approximating the drain current in the strong conduction region of the TFET’s transfer characteristics by a monomial function of the gate voltage. Both methods are illustrated and compared by applying them to measured transfer characteristics of experimental Fin-type TFETs.

28 citations