Pipelined CORDIC processors for generating Gaussian random numbers
TL;DR: A pipelined array for efficient generation of Gaussian random numbers since the direct conversion method is used instead of the central limit theorem method, which requires only one pair of uniformly distributed sequence as its input.
About: This article is published in Signal Processing.The article was published on 1999-02-01. It has received 8 citations till now. The article focuses on the topics: Sequence & Central limit theorem.
Citations
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04 Dec 2006TL;DR: This work has proposed a CORDIC (co-ordinate rotation digital computer)-based unified windowing architecture to remove the spectral leakage, picket fence effect and resolution problems with different tradeoff between mainlobe and sidelobe in the frequency domain.
Abstract: Frequency analysis using DFT (discrete Fourier transform) or its faster computational technique (FFT) is an obvious choice for the entire image and signal processing domain where spectral leakage or picket fence effect is a major problem. Earlier works describe the software and ROM-based implementation of windowing functions to overcome the above-mentioned problems during spectral analysis. In this work we have proposed a CORDIC (co-ordinate rotation digital computer)-based unified windowing architecture to remove the spectral leakage, picket fence effect and resolution problems with different tradeoff between mainlobe and sidelobe in the frequency domain. A parallel-pipelined architecture has been adopted for the present design to ensure high throughput for real-time applications with the latency equal to twice of CORDIC length plus three extra cycles. This unified architecture includes a combination of linear CORDIC and circular CORDIC with FIFO and a few multiplexers where the selection of window and its length are user defined. We have synthesised this architecture with 0.18 μm CMOS technology using Synopsys Design Analyser. The total estimated dynamic power was found to be 350 mW with an operating frequency of 125 MHz and total cell area 11 mm2 (approximately).
34 citations
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05 Jun 2013TL;DR: An efficient hardware implementation of Gaussian Random Number (GRN) generator based upon Box-Muller (BM) and CORDIC algorithms is presented and a novel hardware architecture with flexible design space that unifies the two algorithms is illustrated.
Abstract: An efficient hardware implementation of Gaussian Random Number (GRN) generator based upon Box-Muller (BM) and CORDIC algorithms is presented. We will illustrate a novel hardware architecture with flexible design space that unifies the two algorithms. A major advantage of this work is that unlike any of the previously reported architectures, it is possible to eliminate hardware multipliers and memory blocks in the synthesized hardware. This is achieved without compromising on statistical accuracy of GRN generators which is proved both through error analysis and standard tests. We will also demonstrate two different hardware implementations that vary in terms of speed, tail accuracy (4.7σ to 9.4σ), and utilization of hardware resources such as DSP blocks, logic slices and memory blocks on FPGAs. Finally, we will present a comparison of designed architectures with previously published hardware GRN generators.
9 citations
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TL;DR: This paper presents a high throughput VLSI architecture for Blackman windowing, designed using major blocks like CORDIC and Han-Carlson adder so that a single chip can be used for those applications, where variable length is required.
Abstract: This paper presents a high throughput VLSI architecture for Blackman windowing. Since most of the implementation of windowing functions for real time applications, are based on either ROM or DSP processor. Here the proposed architecture is designed using major blocks like CORDIC(CO-ordinate Rotation DIgital Computer) and Han-Carlson adder. This architecture is flexible in terms of window length. So that a single chip can be used for those applications, where variable length is required. The synthesized result of 16-bit word size architecture with commercially available 0.18µm CMOS technology using Synopsys Design Analyzer, shows that the throughput of this architecture is 400Msamples/s with core area of 21mm2 .
6 citations
Cites methods from "Pipelined CORDIC processors for gen..."
...The CORDIC algorithm is an iterative method to compute rotation of two dimensional vectors and to evaluate the magnitude and angle of rotated vector....
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01 Feb 2014
TL;DR: CORDIC (CO-ordinate Rotation DIgital Computer) based VLSI architecture for implementing Kaiser-Bessel window has been proposed for real time applications and the parallel-pipelined technique has been adopted for the present design to ensure high throughput.
Abstract: Windowing techniques have been widely used for preprocessing of samples before fast Fourier transform (FFT) in real time spectral analysis to minimize spectral leakage and picket fence effect. Among all popular window functions, Kaiser-Bessel window is an obvious choice for its better spectral characteristics. In this paper, CORDIC (CO-ordinate Rotation DIgital Computer) based VLSI architecture for implementing Kaiser-Bessel window has been proposed for real time applications. The parallel-pipelined technique has been adopted for the present design to ensure high throughput. Various architectural design and implementation issues have been discussed. The physical synthesis for ASIC implementation of proposed architecture using Synopsys design compiler(Design Vision) and commercially available 0. 18 μm CMOS yields the core area of 52 mm 2and worst case dynamic power of 890 mW at an operating frequency and voltage of 400 MHz and 1.8 V respectively.
6 citations
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05 Nov 2007TL;DR: A hardware efficient and flexible ASIC (application specific integrated circuit) architecture for Blackman windowing using CORDIC (co-ordinate rotation digital computer) as building block to minimize the spectral leakage and picket fence effect which are usual phenomena during spectral analysis by truncating input signals for finite length of FFT processor.
Abstract: Onus of this work is to propose a hardware efficient and flexible ASIC (application specific integrated circuit) architecture for Blackman windowing using CORDIC (co-ordinate rotation digital computer) as building block to minimize the spectral leakage and picket fence effect which are usual phenomena during spectral analysis by truncating input signals for finite length of FFT processor. A purely pipelined architecture has been adopted for the present design to ensure high throughput for real time applications with the latency equal to twice of the number of CORDIC stages plus two. The magnificence of this architecture is that window length can be changed by users for their specific applications and can be updated online for real time applications. The synthesized result of this 16 bit word size architecture with commercially available 0.18 mum CMOS technology using Synopsys Design Analyzer, shows that total estimated dynamic power to be 152 mW with an operating frequency of 125 MHz and total core area 8 mm2 (approx.)
4 citations
Cites background or methods from "Pipelined CORDIC processors for gen..."
...This work at the beginning presents expression for Blackman windowing functions, and then, mapping that expression to the architecture for pipelined hardware implementation [7]....
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...B. Proposed Blackman window architecture As equation (2) requires trigonometric computations and multiplication with constant coefficients bo, b, and b2, circular and linear CORDIC with pipelined version [7] have been implemented for high throughputs as shown in Fig.2 ....
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References
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01 Jan 1975TL;DR: Feyman and Wing as discussed by the authors introduced the simplicity of the invariant imbedding method to tackle various problems of interest to engineers, physicists, applied mathematicians, and numerical analysts.
Abstract: sprightly style and is interesting from cover to cover. The comments, critiques, and summaries that accompany the chapters are very helpful in crystalizing the ideas and answering questions that may arise, particularly to the self-learner. The transparency in the presentation of the material in the book equips the reader to proceed quickly to a wealth of problems included at the end of each chapter. These problems ranging from elementary to research-level are very valuable in that a solid working knowledge of the invariant imbedding techniques is acquired as well as good insight in attacking problems in various applied areas. Furthermore, a useful selection of references is given at the end of each chapter. This book may not appeal to those mathematicians who are interested primarily in the sophistication of mathematical theory, because the authors have deliberately avoided all pseudo-sophistication in attaining transparency of exposition. Precisely for the same reason the majority of the intended readers who are applications-oriented and are eager to use the techniques quickly in their own fields will welcome and appreciate the efforts put into writing this book. From a purely mathematical point of view, some of the invariant imbedding results may be considered to be generalizations of the classical theory of first-order partial differential equations, and a part of the analysis of invariant imbedding is still at a somewhat heuristic stage despite successes in many computational applications. However, those who are concerned with mathematical rigor will find opportunities to explore the foundations of the invariant imbedding method. In conclusion, let me quote the following: "What is the best method to obtain the solution to a problem'? The answer is, any way that works." (Richard P. Feyman, Engineering and Science, March 1965, Vol. XXVIII, no. 6, p. 9.) In this well-written book, Bellman and Wing have indeed accomplished the task of introducing the simplicity of the invariant imbedding method to tackle various problems of interest to engineers, physicists, applied mathematicians, and numerical analysts.
3,249 citations
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TL;DR: In this paper, the evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, is reviewed.
Abstract: The evolution of CORDIC, an iterative arithmetic computing algorithm capable of evaluating various elementary functions using a unified shift-and-add approach, and of CORDIC processors is reviewed. A method to utilize a CORDIC processor array to implement digital signal processing algorithms is presented. The approach is to reformulate existing DSP algorithms so that they are suitable for implementation with an array performing circular or hyperbolic rotation operations. Three categories of algorithm are surveyed: linear transformations, digital filters, and matrix-based DSP algorithms. >
492 citations
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TL;DR: This paper presents new, fast hardware for computing the exponential function, sine, and cosine by using low-precision arithmetic components to approximate high precision computations, and to correct very quickly the approximation error periodically.
Abstract: This paper presents new, fast hardware for computing the exponential function, sine, and cosine. The main new idea is to use low-precision arithmetic components to approximate high precision computations, and then to correct very quickly the approximation error periodically so that the effect is to get high precision computation at near low-precision speed. The algorithm used in the paper is a nontrivial modification of the well-known CORDIC algorithm, and might be applicable to the computation of other functions than the ones presented.
88 citations