Placement Solution for Homogeneous FPGA Using Tree-Based Algorithm
01 Aug 2018-
TL;DR: A Tree-based placement algorithm for Homogeneous FPGAs is presented and it is shown that by applying the algorithm on a set of benchmark circuits, the placement cost is effectively reduced.
Abstract: Nowadays, FPGA Placement problems have become more complicated since they need to account area constraint and time constraint. Placement is still one of the most difficult problems as the FPGA designs become larger and more complex. As FPGAs are programmable in nature they are an ideal fit for many different markets such as Aerospace, Defense, Audio, Automotive, Broadcast, Industrial, Medical, Security, Video & Image Processing, Wired & Wireless communications. Also, FPGA is becoming popular among big companies and researchers who apply FPGA to highperformance computing and deep learning as it provides better performance, flexible programmability, better cost, etc. In this paper, we present a Tree-based placement algorithm for Homogeneous FPGAs. By applying our algorithm on a set of benchmark circuits we have effectively reduced the placement cost. We have compared results with VPR that uses Simulated annealing approach and our results are comparatively better.
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06 Nov 1994
TL;DR: An accurate and efficient placement routability modeling technique is proposed and incorporated into the prevailing simulated annealing approach based on the supply versus demand analysis of routing resource over an array of regions on a chip.
Abstract: The prevalence of net list synthesis tools raises great concern on routability of cell placement created with state-of-the-art placement techniques. In this paper, an accurate and efficient placement routability modeling technique is proposed and incorporated into the prevailing simulated annealing approach. This accurate and efficient modeling is based on the supply versus demand analysis of routing resource over an array of regions on a chip. Vertical and horizontal routability is analyzed separately due to the bias of routing resource in multiple-metal-layer ASIC designs. A special technique on net bounding box partitioning is also proposed and critical to the accuracy of this modeling at the presence of mega cells, which tend to cause local routing congestion. By incorporating this efficient modeling into the cost function of simulated annealing, experiments conducted on small to large industrial designs indicate that placement routability evaluated with a global router is greatly improved as a result of the proposed accurate modeling.
192 citations
02 Jun 2003
TL;DR: Simulation results show that the proposed routing-aware partitioning-based placement algorithm for FPGAs combined with more accurate delay models and the alignment heuristic can achieve postrouting circuit delays comparable to those obtained from TVPR, while achieving a fourfold speedup in total placement runtime.
Abstract: In this paper we propose a partitioning-based algorithm for FPGAs The method incorporates simple, but effective heuristics that target delay minimization The placement engine incorporates delay estimations obtained from previously placed and routed circuits using VPR according to V Betz and J Rose (1997) As a result, the delay predictions during placement more accurately resemble those observed after detailed routing, which in turn leads to better delay optimization An efficient terminal alignment heuristic for delay minimization is employed to further optimize the delay of the circuit in the routing phase Simulation results show that the proposed technique can achieve comparable circuit delays (after routing) to those obtained with VPR while achieving a 7-fold speedup in placement runtime
91 citations
"Placement Solution for Homogeneous ..." refers methods in this paper
...[4] In 2016, Ryan Pattison presented Gplace tool for Ultra-...
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TL;DR: Simulation results show that the proposed routing-aware partitioning-based placement algorithm for FPGAs combined with more accurate delay models and the alignment heuristic can achieve postrouting circuit delays comparable to those obtained from TVPR, while achieving a fourfold speedup in total placement runtime.
Abstract: In traditional field programmable gate array (FPGA) placement methods, there is virtually no coupling between placement and routing. Performing simultaneous placement and detailed routing has been shown to generate much better placement qualities, but at the expense of significant runtime penalties (Nag and Rutenbar, 1998). We propose a routing-aware partitioning-based placement algorithm for FPGAs in which a looser but effective coupling between the placement and routing stages is used. The placement engine incorporates a more accurate FPGA delay model and employs effective heuristics that minimize circuit delay. Delay estimations are obtained from routing profiles of selected circuits that are placed and routed using the timing-driven versatile place and route (TVPR) (Betz and Rose, 1997), (Marquardt et al., 2000). As a result, the delay predictions during placement more accurately resemble those observed after detailed routing, which in turn leads to better delay optimization. An efficient terminal alignment heuristic for delay minimization is applied during placement to further optimize the delay of the circuit. These two techniques help maintain harmony between placement and routing-delay optimization stages. Simulation results show that the proposed partitioning-based placement combined with more accurate delay models and the alignment heuristic can achieve postrouting circuit delays comparable to those obtained from TVPR, while achieving a fourfold speedup in total placement runtime. In another experiment, we augmented the original TVPR algorithm with the terminal alignment heuristic, and achieved, on average, a 5% improvement in circuit delay with negligible runtime penalty.
76 citations
TL;DR: This work presents an analytic placement method based on a near-linear net model, called star+.
63 citations
"Placement Solution for Homogeneous ..." refers methods in this paper
...Areibi proposed a near-linear analytical model STAR+ used for estimating wire length.[8]...
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10 Oct 2005
TL;DR: This paper incorporates multiple iterations of equation solving process together with a technique for pulling nodes out of the dense area while minimizing linear wire length to present QPF, a quadratic placement tool for FPGAs.
Abstract: In this paper we present QPF, a quadratic placement tool for FPGAs. Quadratic placement algorithms try to minimize total squared wire length by solving linear equations. The resulting placement tends to locate all cells near the center of the chip with a large amount of overlap. Also, since squared wire length is only an indirect measure of linear wire length, the resulting total wire length may not be minimized. We propose methods to alleviate the above two problems that give high quality results while minimizing the total run time. We incorporate multiple iterations of equation solving process together with a technique for pulling nodes out of the dense area while minimizing linear wire length. Experimental results using twenty MCNC benchmark circuits show that, on average, QPF is 5.8 times faster compared to a well known FPGA placement tool VPR, while providing almost comparable estimated total wire length.
55 citations
"Placement Solution for Homogeneous ..." refers methods in this paper
...[6] In 2006, Padmini Gopalakrishnan presented an architecture-aware FPGA placement CAPRI using metric embedding....
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