Patent•
Plated copper interconnect structure
15 May 1997-
TL;DR: In this article, a high conductivity interconnect structure is formed by electroplating or electroless plating of Cu or a Cu-base alloy on a seed layer comprising an alloy of a catalytically active metal such as Cu, and a refractory metal, such as Ta.
Abstract: A high conductivity interconnect structure is formed by electroplating or electroless plating of Cu or a Cu-base alloy on a seed layer comprising an alloy of a catalytically active metal, such as Cu, and a refractory metal, such as Ta. The seed layer also functions as a barrier/adhesion layer for the subsequently plated Cu or Cu-base alloy. Another embodiment comprises initially depositing a refractory metal barrier layer before depositing the seed layer.
Citations
More filters
Patent•
01 Aug 2008
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.
1,501 citations
Patent•
12 Feb 1998TL;DR: In this paper, a conductive interconnect is formed in a semiconductor device by depositing a dielectric layer (28 ) on the semiconductor substrate, and a tantalum nitride barrier layer is then formed within the interconnect opening.
Abstract: In one embodiment, a conductive interconnect ( 38 ) is formed in a semiconductor device by depositing a dielectric layer ( 28 ) on a semiconductor substrate ( 10 ). The dielectric layer ( 28 ) is then patterned to form an interconnect opening ( 29 ). A tantalum nitride barrier layer ( 30 ) is then formed within the interconnect opening ( 29 ). A catalytic layer ( 31 ) comprising a palladium-tin colloid is then formed overlying the tantalum nitride barrier layer ( 30 ). A layer of electroless copper ( 32 ) is then deposited on the catalytic layer ( 31 ). A layer of electroplated copper ( 34 ) is then formed on the electroless copper layer ( 32 ), and the electroless copper layer ( 32 ) serves as a seed layer for the electroplated copper layer ( 34 ). Portions of the electroplated copper layer ( 34 ) are then removed to form a copper interconnect ( 38 ) within the interconnect opening ( 29 ).
287 citations
Patent•
27 Aug 2007
TL;DR: In this paper, a method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the wafer was proposed, where electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
Abstract: A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
286 citations
Patent•
27 Oct 2003
TL;DR: In this paper, a process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is described, which includes the forming of an ultra-thin metal seed layer on the barrier layer.
Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.
240 citations
Patent•
07 Apr 2003
238 citations
References
More filters
TL;DR: In this article, a technique was developed for highly efficient postionization of sputtered metal atoms from a magnetron cathode, based on conventional magnetron sputtering with the addition of a high density, inductively coupled rf (RFI) plasma in the region between the sputtering cathode and the sample.
Abstract: A technique has been developed for highly efficient postionization of sputtered metal atoms from a magnetron cathode. The process is based on conventional magnetron sputtering with the addition of a high density, inductively coupled rf (RFI) plasma in the region between the sputtering cathode and the sample. Metal atoms sputtered from the cathode due to inert gas ion bombardment transit the rf plasma and can be ionized. The metal ions can then be accelerated to the sample by means of a low voltage dc bias, such that the metal ions arrive at the sample at normal incidence and at a specified energy. The ionization fraction, measured with a gridded mass‐sensitive energy analyzer is low at 5 mTorr and can reach 85% at 30 mTorr. Optical emission measurements show scaling of the relative ionization to higher discharge powers. The addition of large fluxes of metal atoms tends to cool the Ar RFI plasma, although this effect depends on the chamber pressure and probably the pressure response of the electron tempera...
376 citations
Patent•
IBM1
TL;DR: In this article, a planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established, and the first layer then is covered by an etch stop material.
Abstract: Patterned conductive lines are formed simultaneously with stud via connections through an insulation layer to previously formed underlying patterned conductive lines in multilevel VLSI chip technology. A first planarized layer of insulation is deposited over a first level of patterned conductive material to which contacts are to be selectively established. The first layer then is covered by an etch stop material. Contact holes are defined in the etch stop material at locations where stud connectors are required. The first layer of insulation is not etched at this time. Next, a second planarized layer of insulation, is deposited over the etch stop material. The second layer insulation, in turn, is etched by photolithography down to the etch stop material to define desired wiring channels, some of which will be in alignment with the previously formed contact holes in the etch stop material. In those locations where the contact holes are exposed, the etching is continued into the first layer of insulation to uncover the underlying first level of patterned conductive material. The channels and via holes are overfilled with metallization. The excess metallization is removed by etching or by chem-mech (chemical-mechanical) polishing.
362 citations
IBM1
TL;DR: The Dual Damascene as mentioned in this paper is a planar, monolithic-metal interconnect, comprising a vertical metal stud and horizontal metal interconnect embedded in an insulator matrix, and it was successfully implemented in the manufacture of IBM's 4-Mb DRAM.
Abstract: Escalating density, performance, and (perhaps most importantly) manufacturing requirements associated with ULSI semiconducting wiring, necessitate a metamorphosis in interconnection technology. To meet these needs, an inlaid fully integrated wiring technology called Dual Damascene has been designed and demonstrated at IBM's Essex Junction, Vermont, facility. A subset of the technology's features has been successfully implemented in the manufacture of IBM's 4-Mb DRAM. The Dual Damascene structure achieved is a planar, monolithic-metal interconnect, comprising a vertical metal stud and horizontal metal interconnect, both embedded in an insulator matrix. The complete Dual Damascene technology features a unique process sequence, chemical-mechanical insulator planarization, stacked photolithographic masks, clustered stud and interconnect etch, concurrent stud and interconnect metal fill, and chemical-mechanical metal etchback. >
190 citations
Patent•
08 Oct 1991TL;DR: Alkali-free layers of pure metals such as copper, nickel, and cobalt were deposited on noble metal or noble metal sensitized substrates by electroless deposition using pure quaternary ammonium hydroxides or quaternaries phosphonium hyroxides to generate the hydroxyl ion (OH - ) needed to produce electrons for the metal reduction.
Abstract: Alkali-free layers of pure metals such as copper, nickel and cobalt were deposited on noble metal or noble metal sensitized substrates by electroless deposition using pure quaternary ammonium hydroxides or quaternary phosphonium hydroxides to generate the hydroxyl ion (OH - ) needed to produce electrons for the metal reduction. Using the new alkaline-free electroless compositions, uniform, continuous and reproducible metal layers were selectively deposited with excellent electrical properties. With the improved compositions and process, nanosize copper lines having widths in the range of 100 to 500 nm were prepared.
183 citations
TL;DR: In this paper, a simple model for ionization of sputtered metals by a high-density plasma is presented, and ion flux fractions of greater than 80% can be obtained by sputtering aluminum into a region of dense plasma (ne∼1012 cm−3).
Abstract: A simple model for ionization of sputtered metals by a high‐density plasma is presented. Experimentally, ion flux fractions of greater than 80% can be obtained by sputtering aluminum into a region of dense plasma (ne∼1012 cm−3). Such a process has important applications in the filling of high‐aspect‐ratio features encountered in microelectronics fabrication. Both electron‐impact and Penning ionization mechanisms are considered in this model. Under conditions of low electron density (ne≪1011 cm−3), Penning ionization is found to be the dominant ionization path. This is consistent with the accepted ionization mechanism for conventional diode sputtering. When high electron densities are generated, however, electron‐impact ionization plays a significant ionization role. Langmuir probe measurements of the inductively coupled plasma indicate that the electron density lies between 2×1011 and 2×1012 cm−3. The model, in combination with measured plasma density, is used to calculate ion fractions. Modeled and exper...
165 citations