Proceedings ArticleDOI
Power aware minimization of complementary logic functions based on maximal HD
Padmanabhan Balasubramanian,Y. Sirisha +1 more
- pp 125-129
Reads0
Chats0
TLDR
This work considers the problem of logic minimization for a special class of Boolean networks, targeting low power implementation, using static CMOS logic, and frames a new binary minterm-value matrix/binary max term-value (BMV) matrix for a binary 2-tuple.Abstract:
In this work, the authors consider the problem of logic minimization for a special class of Boolean networks, targeting low power implementation, using static CMOS logic. The authors start by framing a new binary minterm-value (BmV) matrix/binary max term-value (BMV) matrix for a binary 2-tuple, [mi (Mi), mj (Mj)], where HD (mi (Mi), mj (Mj)) is O(n), where n represents the support of a Boolean function. The quality of the resulting circuits, evaluated on the basis of established cost metrics for a modest 0.35mu TSMC CMOS process, demonstrate average savings in power by 14.39% for the samples mentioned in this paper, besides reduction in gate and literal count by 36.59% and 11.35% respectively, over the best of existing methodsread more
References
More filters
Book
Switching and Finite Automata Theory
Zvi Kohavi,Niraj K. Jha +1 more
TL;DR: Theories are made easier to understand with 200 illustrative examples, and students can test their understanding with over 350 end-of-chapter review questions.
Journal ArticleDOI
Two-level logic minimization: an overview
TL;DR: This paper exposes the classical approach for two-level logic minimization, and presents the recent developments that overcome the limitations of the procedures proposed in the past, and reveals a minimizer that is 10 up to 50 times faster than the previously best known ones, and that is able to handle more complex functions.
Book
Logic Synthesis
TL;DR: Logic synthesis transforms RTL code into a gate-level netlist RTL Verilog converted into Structural Verilogs and shows how the structure of theVerilog affects the semantics of the text itself.
Book
Logic Synthesis for Asynchronous Controllers and Interfaces
TL;DR: This book is devoted to logic synthesis and design techniques for asynchronous circuits and uses the mathematical theory of Petri Nets and asynchronous automata to develop practical algorithms implemented in a public domain CAD tool.
Journal ArticleDOI
Gate-level power estimation using tagged probabilistic simulation
TL;DR: A probabilistic simulation technique to estimate the power consumption of a CMOS circuit under a general delay model based on the notion of a tagged (probability) waveform, which models the set of all possible events at the output of each circuit node.