Power Conversion With SiC Devices at Extremely High Ambient Temperatures

TLDR: In this article, the capability of SiC power semiconductor devices, in particular JFET and Schottky barrier diodes (SBDs), for application in high-temperature power electronics was evaluated.

Abstract: This paper evaluates the capability of SiC power semiconductor devices, in particular JFET and Schottky barrier diodes (SBD) for application in high-temperature power electronics. SiC JFETs and SBDs were packaged in high temperature packages to measure the dc characteristics of these SiC devices at ambient temperatures ranging from 25degC (room temperature) up to 450degC. The results show that both devices can operate at 450degC, which is impossible for conventional Si devices, at the expense of significant derating. The current capability of the SiC SBD does not change with temperature, but as expected the JFET current decreases with rising temperatures. A 100 V, 25 W dc-dc converter is used as an example of a high-temperature power-electronics circuit because of circuit simplicity. The converter is designed and built in accordance with the static characteristics of the SiC devices measured under extremely high ambient temperatures, and then tested up to an ambient temperature of 400degC. The conduction loss of the SiC JFET increases slightly with increasing temperatures, as predicted from its dc characteristics, but its switching characteristics hardly change. Thus, SiC devices are well suited for operation in harsh temperature environments like aerospace and automotive applications.

Figures

Fig. 2. Experimental setup for measuring temperature dependency of the SiC JFET dc characteristics.

TABLE III TRADEOFFS IN DESIGNING HIGH TEMPERATURE CONVERTER

Fig. 5. Temperature dependency of the dc characteristics for the SiC SBD. (a) V -I characteristics, (b) forward voltage drop (V ) for I = 0:5 A, (c) reverse leakage and break down characteristics.

Fig. 6. Experimental setup for extremely high temperature operation of the SiC dc-dc buck converter.

TABLE I SIC DEVICE PARAMETERS

Fig. 7. Comparison between SiC devices and Si devices at room temperature (25 C). (a) V (SiC-JFET/Si-MOSFET), (b) I (SiC-JFET/Si-MOSFET), (c) V (SiC-SBD/Si-FRD), (d) I (SiC-SBD/Si-FRD).

Frequently asked questions

Q1. What have the authors contributed in "Power conversion with sic devices at extremely high ambient temperatures" ?

This paper evaluates the capability of SiC power semiconductor devices, in particular JFET and Schottky barrier diodes ( SBD ) for application in high-temperature power electronics. 

Q2. What is the effect of the reduction of the peak value in the transient current with rising temperatures?

The reduction of the peak value in the transient current with rising temperatures results in a reduction of the saturated drain current with the excess current attributed to circuit parasitic capacitance components. 

Q3. What is the effect of the temperature on the diode?

The cut-in voltage of the diode decreases with rising temperatures due to the Schottky barrier height reduction with increasing temperature. 

Q4. Why does the forward voltage drop change with increasing temperatures?

The forward voltage drop changes nonlinearly due to the adverse effects of the cut-in voltage and series resistance changes with rising temperatures. 

Q5. What is the voltage drop at the non-conduction interval?

The imposed voltage during the non-conduction interval decreases a few Volts at high temperatures because the voltage drop across the SiC JFET increases with increasing ambient temperatures. 

Q6. What is the output voltage at 400 C?

The output voltage decreases approximately by 5 V at 400 C from its value at room temperature, but the reduction is relatively small for high output voltages. 

Q7. What is the voltage of the gate driver applied to the SiC JFET?

The gate driver voltage applied to the SiC JFET is V for the “ON” condition and V for the “OFF” condition, which is lower than the threshold gate voltage of V at 450 C. 

Q8. What is the effect of the SiC JFET on the turn-on behavior?

The turn-on behavior of the SiC JFET is affected by the switching behavior of the SiC SBD while the turn-off behavior is dominated by the SiC JFET itself. 

Q9. What is the peak value of the drain current at the turn-on instant?

The peak value of the transient current at the turn-on instant decreases with increasing ambient temperatures, but it exceeds the saturated drain current of the SiC JFET (i.e., a peak current of 1.2 A and a saturated current of 0.7 A for the 400 C case). 

Q10. How much is the peak switching loss of the SiC JFET?

The peak switching loss of the SiC JFET increases with temperature rise, and it becomes 1.6 times at 400 C of the value at room temperature. 

Q11. What was the wire bonding method used for the SBD anode contacts?

The JFET source and gate contacts and the SBD anode contacts were wire bonded to the respective terminals in the package with 3-mil Al wire. 

Q12. What is the leakage current in the “OFF” condition of the SiC JFET?

It shows that the SiC JFET can remain in the “OFF” condition at 400 C, but the leakage current increases remarkably when the temperature exceeds 300 C. 

Q13. What temperature range was the operation of the converter?

The operation of the devices were confirmed and evaluated for the converter operating from 25 C (room temperature) to extremely high ambient temperatures ( C). 

Q14. What is the voltage and current of the SiC JFET?

Fig. 8(a) shows the drain-source voltage for the SiC JFET indicating that it can remain in the “OFF” condition when applying a gate voltage of V for a of 100 V regardless of the ambient temperature. 

Q15. What is the voltage drop between the drain and source at 0.5 A?

From Fig. 4(a) the voltage drop between the drain and source at 0.5 A changes from 0.7 V at 25 C to 6 V at 450 C. Fig. 4(c) shows drain-source resistance as function of temperature for A at the “ON” condition. 

Q16. What causes the spike voltages and currents at the top and bottom of the waveform?

The spike voltages and currents observed at the top and bottom of the waveform in Fig. 8(b), (d), and (e) are caused by the switching operations of the SiC JFET and SBD as well as the parasitic components from the long wires used for the main circuit and the measurements.