Power distribution system design methodology and capacitor selection for modern CMOS technology
TL;DR: In this paper, the impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models.
Abstract: Power systems for modern complementary metal-oxide-semiconductor (CMOS) technology are becoming harder to design. One design methodology is to identify a target impedance to be met across a broad frequency range and specify components to meet that impedance. The impedance versus frequency profiles of the power distribution system components including the voltage regulator module, bulk decoupling capacitors and high frequency ceramic capacitors are defined and reduced to simulation program with integrated circuit emphasis (SPICE) models. A sufficient number of capacitors are placed in parallel to meet the target impedance. Ceramic capacitor equivalent series resistance (ESR) and ESL are extremely important parameters in determining how many capacitors are required. SPICE models are then analyzed in the time domain to find the response to load transients.
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935 citations
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289 citations
TL;DR: In this article, the authors provide an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.
Abstract: The power consumption of microprocessors is increasing at an alarming rate leading to 2X reduction in the power distribution impedance for every product generation. In the last decade, high I/O ball grid array (BGA) packages have replaced quad flat pack (QFP) packages for lowering the inductance. Similarly, multilayered printed circuit boards loaded with decoupling capacitors are being used to meet the target impedance. With the trend toward system-on-package (SOP) architectures, the power distribution needs can only increase, further reducing the target impedance and increasing the isolation characteristics required. This paper provides an overview on the design of power distribution networks for digital and mixed-signal systems with emphasis on design tools, decoupling, measurements, and emerging technologies.
259 citations
TL;DR: In this article, the authors reviewed possible solutions based on decoupling or isolation for suppressing power distribution network (PDN) noise on package or printed circuit board (PCB) levels.
Abstract: Mitigating power distribution network (PDN) noise is one of the main efforts for power integrity (PI) design in high-speed or mixed-signal circuits. Possible solutions, which are based on decoupling or isolation concept, for suppressing PDN noise on package or printed circuit board (PCB) levels are reviewed in this paper. Keeping the PDN impedance very low in a wide frequency range, except at dc, by employing a shunt capacitors, which can be in-chip, package, or PCB levels, is the first priority way for PI design. The decoupling techniques including the planes structure, surface-mounted technology decoupling capacitors, and embedded capacitors will be discussed. The isolation approach that keeps part of the PDN at high impedance is another way to reduce the PDN noise propagation. Besides the typical isolation approaches such as the etched slots and filter, the new isolation concept using electromagnetic bandgap structures will also be discussed.
200 citations
References
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IBM1
TL;DR: In this article, the design of IBM's S/390 computer for control of mid-frequency noise is discussed, where the power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits.
Abstract: Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBM's CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.
93 citations
IBM1
TL;DR: Capacitor values and quantities are calculated using time and frequency domain techniques in this article, where the authors propose a method for decoupling capacitors to reduce EMC/EMI radiated noise.
Abstract: CMOS circuits on printed circuit boards with continuous power planes require decoupling capacitors to keep power supply within specification, provide signal integrity and reduce EMC/EMI radiated noise. Capacitor values and quantities are calculated using time and frequency domain techniques.
92 citations
26 Oct 1998
TL;DR: In this article, a new technique to extract ESR of decoupling capacitors is described, and a study that compares the ESL of different pad layout geometries is also presented.
Abstract: Power distribution system noise affects computer product timing performance, signal integrity and electromagnetic interference. Between 1 MHz and 1 GHz, the primary means of reducing power distribution noise is with ceramic decoupling capacitors. To achieve a certain target impedance, it is important to characterize the ESR of ceramic decoupling capacitors, as this directly determines the number of capacitors required on a board. A new technique to extract ESR is described in this paper. Another factor which determines the capacitance value of decoupling capacitors is the ESL (equivalent series inductance) associated with capacitors mounted on a PCB. A study that compares the ESL of different pad layout geometries is also presented.
53 citations
27 Oct 1997
TL;DR: In this paper, the authors consider the resonance between chip capacitance and package inductance, and the key parameters for package power are the core power supply loop inductance and the inductances and resistance used to connect any decoupling capacitors on the package.
Abstract: The power distribution system will become an increasingly important package design consideration for computer systems such as the Sun Microsystems desktop workstation, at least as important as simultaneous switch. Power distribution impedance is controlled by the switching power supply, bulk capacitance, ceramic capacitance and power plane properties at various portions of the frequency spectrum. A major concern with package power is resonance between chip capacitance and package inductance. The key parameters for package power are the core power supply loop inductance and the inductance and resistance used to connect any decoupling capacitors on the package. Decoupling capacitors on the package can be used but they will not be effective unless the connections to them are specially designed using aggressive technologies.
37 citations
26 Oct 1998
TL;DR: In this paper, thin film decoupling capacitors with a novel structure were modeled and their performance simulated and the influences of contact configurations and dielectric and metal layer thicknesses on the impedance behavior were studied.
Abstract: Thin film decoupling capacitors with a novel structure were modeled and their performance simulated. The influences of contact configurations and dielectric and metal layer thicknesses on the impedance behaviour were studied. Simulation shows that thin film capacitors have excellent high frequency properties.
8 citations