Book ChapterDOI
Power-Efficient Bidirectional Shift Register Using Conditional Bidirectional Pulsed Latch Circuit
Karan Kumar,Vaithiyanathan Dhandapani +1 more
- pp 123-130
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TLDR
In this paper, a modified circuit is implemented in 28 nm CMOS technology with a bidirectional shift register with pulsed latch circuit with feedback and the power reduction is compared with master-slave flip-flop.Abstract:
In complementary metal–oxide–semiconductor (CMOS) logic circuits, the main design requirement for low-power applications is to reduce the power dissipation. Dynamic power dissipation occurs in clock network which contributes up to 30–45% of total power dissipation of circuit mostly because of flip-flop are being used for sequencing which consumes lot of power therefore to reduce the power consumption flip-flop are being replaced with pulsed latch circuit with feedback. Conditional circuit is used in bidirectional shift register with bidirectional pulsed latch circuit. When it is compared with master–slave flip-flop, power reduction is 38%. Modified circuit is being implemented in 28 nm CMOS technology.read more
References
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Journal ArticleDOI
Metastability of CMOS latch/flip-flop
Lee-Sup Kim,Robert W. Dutton +1 more
TL;DR: In this article, the authors used the AC small-signal analysis in the frequency domain instead of the usual time-domain approach to obtain the optimal device size, aspect ratio, and configurations for the design of the metastable hardened CMOS latch/flip-flops.
Journal ArticleDOI
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy
TL;DR: New techniques to evaluate the energy and delay of flip-flop and latch designs are presented and it is shown that no single existing design performs well across the wide range of operating regimes present in complex systems.
Journal ArticleDOI
Low-Power and Area-Efficient Shift Register Using Pulsed Latches
TL;DR: The proposed shift register saves 37% area and 44% power compared to the conventional shift register with flip-flops and uses a small number of the pulsed clock signals instead of the conventional single pulsing clock signal.
Proceedings ArticleDOI
Pulsed-latch aware placement for timing-integrity optimization
TL;DR: A unified placement framework for pulsed-latches to maintain the timing integrity is presented and results show that the placement flow can effectively consider pulse-width integrity and thus achieve much smaller total/worst negative slacks with marginal wirelength overheads, compared to a leading commercial and an academic placement flows.
Journal ArticleDOI
Pulsed-Latch Utilization for Clock-Tree Power Optimization
TL;DR: This is the first paper to propose a migration approach to efficiently construct a clock tree with both pulsed-latches and flip-flops, based on minimum-cost maximum-flow formulation to globally determine the tree topology.