Power Minimization in IC Design:
Principles and Applications
Massoud Pedram
Department of EE-Systems
University of Southern California
Los Angeles CA 90089
Abstract
Low power has emerged as a principal theme in today’s electronics indus-
try. The need for low power has caused a major paradigm shift in which power
dissipation is as important as performance and area. This article presents an
in-depth survey of CAD methodologies and techniques for designing low power
digital CMOS circuits and systems and describes the many issues facing design-
ers at architectural, logic and physical levels of design abstraction. It reviews
some of the techniques and tools that have been proposed to overcome these diffi-
culties and outlines the future challenges that must be met to design low power,
high performance systems.
1. Introduction
In the past, the major concerns of the VLSI designer were area, perfor-
mance, cost and reliability; power considerations were mostly of only secondary
importance. In recent years, however, this has begun to change and, increasingly,
power is being given comparable weight to area and speed. Several factors have
contributed to this trend. Perhaps the primary driving factor has been the remark-
able success and growth of the class of personal computing devices (portable
desktops, audio- and video-based multimedia products) and wireless communica-
tions systems (personal digital assistants and personal communicators) which
demand high-speed computation and complex functionality with low power con-
sumption.
2 Power Minimization in IC Design: Principles and Applications
In these applications, average power consumption is a critical design con-
cern. The projected power consumption for a portable multimedia terminal when
implemented using off-the-shelf components not optimized for low-power opera-
tion is about 40 W. With advanced Nickel-Metal-Hydride (secondary) battery
technologies yielding around 65 watt-hours/kilogram [113], this terminal would
require an unacceptable 6 kilograms of batteries for 10 hours of operation
between recharges. Even with new battery technologies such as rechargeable lith-
ium ion or lithium polymer cells, it is anticipated that the expected battery life-
time will increase to about 90-110 watt-hours/kilogram over the next 5 years
[113] which still leads to an unacceptable 3.6-4.4 kilograms of battery cells. In
the absence of low-power design techniques then, current and future portable
devices will suffer from either a very short battery life or a very heavy battery
pack.
There also exists a strong pressure for producers of high-end products to
reduce their power consumption. Contemporary performance optimized micro-
processors dissipate as much as 15-30 W at 100-200 MHz cock rates [39]. In the
future, it can be extrapolated that a 10 cm
2
microprocessor, clocked at 500 MHz
(which is a not too aggressive estimate for the next decade) would consume about
300 W. The cost associated with packaging and cooling such devices is huge.
Since core power consumption must be dissipated through the packaging, increas-
ingly expensive packaging and cooling strategies are required. Unless power con-
sumption is dramatically reduced, the resulting heat will limit the feasible
packing and performance of VLSI circuits and systems. Consequently, there is a
clear financial advantage to reducing the power consumed in high performance
systems.
In addition to cost, there is the issue of reliability. High power systems
often run hot; at the same time, high temperature tends to exacerbate several sili-
con failure mechanisms. Every 10 °C increase in operating temperature roughly
doubles failure rate for the components [133]. In this context, peak power (maxi-
mum possible power dissipation) is a critical design factor because it determines
the thermal and electrical limits of designs, impacts the system cost, size and
weight, dictates specific battery type, component and system packaging and heat
sinks, and aggravates the resistive and inductive voltage drop problems. It is
therefore essential to have the peak power under control.
From the environmental viewpoint, the smaller the power dissipation of
electronic systems, the lower the heat pumped into the rooms, the lower the elec-
Power Minimization in IC Design: Principles and Applications 3
tricity consumed and therefore, the less the impact on global environment, the
less the office noise (due to elimination of a fan from the desktop), and the less
stringent the environment/office power delivery and cooling requirements.
The motivations for reducing power consumption differ from application to
application. In the class of micro-powered battery-operated, portable applica-
tions, such as cellular phones and personal digital assistants, the goal is to keep
the battery lifetime and weight reasonable and the packaging cost low. Power lev-
els below 1-2 W, for instance, enable the use of inexpensive plastic packages. For
high performance, portable computers, such as laptop and notebook computers,
the goal is to reduce the power dissipation of the electronics portion of the system
to a point which is about half of the total power dissipation (including that of dis-
play and hard disk). Finally, for high performance, non-battery operated systems,
such as workstations, set-top computers and multimedia information processing
and communication systems, the overall goal of power minimization is to reduce
system cost (cooling, packaging and energy bill) and ensure long-term circuit
reliability. These different requirements impact how power optimization is
addressed and how much the designer is willing to sacrifice in cost or perfor-
mance to obtain lower power dissipation.
Our goal in writing this paper is to provide background and outlook for
people interested in using or developing low power design methodologies and
techniques. Even though we tried to be complete, some research work might have
been unintentionally left out. In addition, the description of various techniques
may be perceived as uneven at times because of the amount of coverage given to
certain topics; this is mainly due to our experience in using these methods for
building our power optimization and synthesis system, POSE.
The paper is organized as follows. First, we describe sources of power dis-
sipation in CMOS circuits and degrees of freedom in the low power design space.
We then present an in-depth survey (and in many cases analysis) of power estima-
tion and minimization techniques and describe some of the frontiers of the
research currently being pursued. We conclude by summarizing the major low
power design challenges that lie ahead.
2. Sources of Power Dissipation
Power dissipation in digital CMOS circuits is caused by four sources as
follows.
4 Power Minimization in IC Design: Principles and Applications
• the leakage current, which is primarily determined by the fabrication
technology, consists of two components: 1) reverse bias current in the
parasitic diodes formed between source and drain diffusions and the
bulk region in a MOS transistor, and 2) the subthreshold current that
arises from the inversion charge that exists at the gate voltages below
the threshold voltage,
• the standby current which is the DC current drawn continuously from
V
dd
to ground,
• the short-circuit (rush-through) current which is due to the DC path
between the supply rails during output transitions,
• the capacitance current which flows to charge and discharge capacitive
loads during logic changes.
The diode leakage is proportional to the area of the source or drain diffu-
sion and the leakage current density and is typically 1 picoA for a 1 micron mini-
mum feature size. The subthreshold leakage current for long channel devices
increases linearly with the ratio of the channel width over channel length and
decreases exponentially with V
GS
- V
t
where V
GS
is the gate bias and V
t
is the
transistor threshold voltage. Several hundred millivolts of “off bias” (say,
300-400 mV) typically reduces the subthreshold current to negligible values. With
reduced power supply and device threshold voltages, the subthreshold current
will however become more pronounced. In addition, at short channel lengths, the
subthreshold current also becomes exponentially dependent on drain voltage
instead of being independent of V
DS
(see [44] for a recent analysis).
The standby power consumption happens, for example, when both the
nMOS and pMOS transistors are continuously on in a pseudo-nMOS inverter,
when the drain of an nMOS transistor is driving the gate of another nMOS tran-
sistor in a pass-transistor logic, or when the tristated input of a CMOS gate leaks
away to a value between V
dd
and ground. The standby power is equal to the prod-
uct of V
dd
and the DC current drawn from the power supply to ground.
The term static power dissipation refers to the sum of leakage and standby
dissipations. Leakage currents in CMOS circuits can be made small with proper
choice of device technology. Standby currents are important in CMOS design
styles like pseudo-nMOS and nMOS pass transistor logic and in memory cores. In
this article, we assume that the standby dissipation is insignificant, thus limiting
ourselves to CMOS technologies, logic styles and circuit structures [63] in which
this condition holds.
Power Minimization in IC Design: Principles and Applications 5
The short-circuit power consumption for an inverter gate is proportional to
the input ramp time, the load and transistor sizes of the gate. The maximum short
circuit current flows when there is no load; this current decreases with the load.
Depending on the approximations used to model the currents and to estimate the
input signal dependency, different formulae [161] [52], with varying accuracy,
have been derived for the evaluation of the short circuit power. A useful formula
was recently derived in [155] that shows the explicit dependence of the short cir-
cuit power dissipation on the design and performance parameters, such as transis-
tor sizes, input and output ramp times and the load. The idea is to adopt an
alternative definition of the short circuit power dissipation, through an equivalent
(virtual) short circuit capacitance C
SC
.
If gate sizes are selected so that the input and output rise/fall times are
about equal, the short-circuit power consumption will be less than 15% of the
dynamic power consumption [161]. If, however, design for high performance is
taken to the extreme where large gates are used to drive relatively small loads and
if the input ramp time is long, then there will be a stiff penalty in terms of
short-circuit power consumption.
The dominant source of power dissipation CMOS circuits is the charging
and discharging of the node capacitances (also referred to as the capacitive power
dissipation) and is given by:
(1)
where C
L
is the physical capacitance at the output of the node, V
dd
is the supply
voltage, E(sw) (referred to as the switching activity) is the average number of out-
put transitions per 1/f
clk
time, and f
clk
is the clock frequency. The product of
E(sw) and f
clk
which is the number of transitions per second, is referred to as the
transition density in [101].
The term dynamic power dissipation refers to the sum of short circuit and
capacitive dissipations. Using the concept of equivalent short-circuit capacitance
described above, the dynamic power dissipation can be calculated using equation
(1) if we add C
SC
to C
L
. Short-circuit currents in CMOS circuits can be made
small with appropriate circuit design techniques. In most of this article, we will
thus focus on capacitive power dissipation.
P
0.5C
L
V
dd
2
Esw()f
cl
k
=
