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Journal ArticleDOI

Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique

24 Jun 2010-IEEE Journal of Solid-state Circuits (IEEE)-Vol. 45, Iss: 7, pp 1365-1379
TL;DR: The “assisted opamp” integrator is introduced, which is a way of achieving low distortion operation with low power consumption and circuit implementations of the technique for single-bit modulators using NRZ and switched-capacitor-resistor feedback DACs are presented.
Abstract: The opamp in the first integrator of a high resolution single-bit continuous-time modulator has stringent slew rate requirements, which increases power dissipation. We introduce the “assisted opamp” integrator, which is a way of achieving low distortion operation with low power consumption. We present circuit implementations of our technique for single-bit modulators using NRZ and switched-capacitor-resistor (SCR) feedback DACs. Audio modulators designed in a 0.18 μm CMOS technology are used as vehicles to demonstrate the effectiveness of our techniques. The modulator with an NRZ DAC achieves a dynamic range of 92.5 dB in a 24 kHz bandwidth and dissipates 110 μW from a 1.8 V supply. A second design, which employs an SCR-DAC, achieves a dynamic range of 91.5 dB and dissipates 122 μW. The figures of merit (FOM) of these modulators, 175.9 dB and 174.4 dB respectively, are comparable with those of state-of-the-art multibit designs.
Citations
More filters
Journal ArticleDOI
TL;DR: A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.
Abstract: This paper presents a tutorial overview of ΣΔ modulators, their operating principles and architectures, circuit errors and models, design methods, and practical issues. A review of the state of the art on nanometer CMOS implementations is described, giving a survey of cutting-edge ΣΔ architectures, with emphasis on their application to the next generation of wireless telecom systems.

235 citations


Additional excerpts

  • ...[74]; CT- Ms [53], [66], [67], [69], [136]....

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Journal ArticleDOI
TL;DR: This work gives a method for stabilizing a single-bit continuous-time delta-sigma modulator that uses an FIR feedback DAC and shows that increasing the number of taps beyond a certain number does not improve performance.
Abstract: Single-bit continuous-time delta-sigma modulators (CTDSM) using FIR feedback DACs inherit the appealing aspects of both single-bit and multibit designs, without the disadvantage of either approaches. In this work, we give a method for stabilizing a CTDSM that uses an FIR feedback DAC. Further, we show that increasing the number of taps beyond a certain number (dependent on the architecture and oversampling ratio of the modulator) does not improve performance. The results of our analysis are incorporated in the design of a third-order audio CTDSM which achieves a peak A-weighted SNR of 102.3 dB (raw SNR of 98.9 dB) and a spurious-free dynamic range of 106 dB in a 24 kHz bandwidth, while consuming only 280 μW from a 1.8 V supply.

104 citations


Cites background or methods from "Power Reduction in Continuous-Time ..."

  • ...[19] and [14] are audio CTDSMs targeting similar specifications in the same process technology....

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  • ...[19] is a multibit design, while [14] is a single-bit CTDSM with the linearity of the first opamp being enhanced by the assisted opamp technique....

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  • ...Thus, no extra resistors are needed to realize and [14]....

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Journal ArticleDOI
TL;DR: The efficacy of the architectural and circuit techniques is borne out by measurement results from a modulator that achieves about 71-dB SNDR in a 36-MHz bandwidth while consuming only 15 mW from a 1.2-V supply.
Abstract: We give design considerations for single-bit continuous-time Delta-Sigma modulators (CTDSMs) with FIR feedback DACs. These modulators have the low jitter sensitivity and high linearity properties characteristic of a multibit modulator, while using a simple one-bit quantizer, thereby combining the advantages of single-bit and multibit operation. We propose a method to compensate the loop for the delay introduced by the FIR-DAC. The efficacy of our architectural and circuit techniques is borne out by measurement results from a modulator that achieves about 71-dB SNDR in a 36-MHz bandwidth while consuming only 15 mW from a 1.2-V supply. Implemented in a 90-nm CMOS process and sampling at 3.6 GS/s, the CTDSM has a figure of merit (FoM) of 72.7 fJ/lvl, while occupying 0.12 mm2.

88 citations


Cites methods from "Power Reduction in Continuous-Time ..."

  • ...Power reduction is achieved in our design by implementing and using the assisted-opamp technique [15], where a replica of the integrator input current is injected into the output of the opamp....

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Journal ArticleDOI
TL;DR: This paper presents the first dynamic zoom ADC, intended for audio applications, which achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW.
Abstract: This paper presents the first dynamic zoom ADC. Intended for audio applications, it achieves 109-dB DR, 106-dB signal-to-noise ratio, and 103-dB SNDR in a 20-kHz bandwidth, while dissipating only 1.12 mW. This translates into the state-of-the-art energy efficiency as expressed by a Schreier FoM of 181.5 dB. It also achieves the state-of-the-art area efficiency, occupying only 0.16 mm2 in the 0.16- $\mu \text{m}$ CMOS. These advances are enabled by the use of concurrent fine and coarse conversions, dynamic error-correction techniques, and a dynamically biased inverter-based operational transconductance amplifier.

68 citations

Journal ArticleDOI
TL;DR: This paper presents an overview of emerging circuits and systems techniques which are at the forefront of the state of the art in ΔΣ modulators, pushing their performance forward and giving rise to new generations of data converters.
Abstract: This paper presents an overview of emerging circuits and systems techniques which are at the forefront of the state of the art in $\Delta\Sigma$ modulators, pushing their performance forward and giving rise to new generations of data converters. Among others, those strategies involving the development of new applications and paradigms—like RF/GHz-range $\Delta\Sigma$ digitisation, digital-assisted embedded loop filters, time-to-digital conversion and hybrid $\Delta\Sigma$ /Nyquist-rate architectures—are discussed, as well as the implications and design challenges derived from their integration in deep nanometer CMOS technologies. The envisioned $\Delta\Sigma$ techniques are presented in a systematic way around the main analog building blocks embedded in a $\Delta\Sigma$ modulator, i.e., the loop filter and the quantizer. Analysing the trends in the design of these blocks allows us to offer perspectives on how $\Delta\Sigma$ converters will evolve in the next years.

67 citations


Cites background or methods from "Power Reduction in Continuous-Time ..."

  • ...Indeed, this technique can be applied to different OTA topologies [22], [23], including two-stage feedforward compensated and Miller-compensated OTAs, featuring state-of-the-art...

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  • ...(CIFF) topology with single-bit quantization [22], [23], [26],...

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  • ...[22] and conceptually illustrated in the single-bit CT- M shown in Fig....

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  • ...CT- M with assisted-opamp integrator proposed in [22]....

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  • ...Note that the most efficient designs are mainly based on CT circuits, some of them featuring a FOMS over 175 dB [22]–[26]....

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References
More filters
Book
08 Nov 2004
TL;DR: This chapter discusses the design and simulation of delta-sigma modulator systems, and some of the considerations for implementation considerations for [Delta][Sigma] ADCs.
Abstract: Chapter 1: Introduction.Chapter 2: The first-order delta-sigma modulator.Chapter 3: The second-order delta-sigma modulator.Chapter 4: Higher-order delta-sigma modulation.Chapter 5: Bandpass and quadrature delta-sigma modulation.Chapter 6: Implementation considerations for [Delta][Sigma] ADCs.Chapter 7: Delta-sigma DACs.Chapter 8: High-level design and simulation.Chapter 9: Example modulator systems.Appendix A: Spectral estimation.Appendix B: The delta-sigma toolbox.Appendix C: Noise in switched-capacitor delta-sigma data converters.

2,200 citations


"Power Reduction in Continuous-Time ..." refers methods in this paper

  • ...Since the noise performance is dominated by thermal noise, it is also relevant to compute the FOM proposed by Schreier [12] given by Note that is a logarithmic measure....

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  • ...Since the noise performance is dominated by thermal noise, it is also relevant to compute the FOM proposed by Schreier [12] given by...

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Journal ArticleDOI
TL;DR: In this paper, a /spl Delta/spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described, which is effective even for very low oversampling ratios, and can be used for any modulation order.
Abstract: A /spl Delta//spl Sigma/ topology with reduced sensitivity to opamp nonlinearities is described. The technique is effective even for very low oversampling ratios, and can be used for any modulation order. Techniques for reducing other nonideal effects are also proposed.

575 citations


"Power Reduction in Continuous-Time ..." refers methods in this paper

  • ...The discussion in Section I indicates that the design of the first integrator with adequate linearity and low power dissipation represents a significant challenge in the design of high performance single bit CTDSMs....

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  • ...This technique was applied to the design of audio-frequency third-order CTDSMs (with NRZ and SCR feedback DACs) implemented in a 0.18 m CMOS technology....

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  • ...This technique, originally proposed to reduce distortion in discretetime DSMs [8] is adopted in our continuous-time design....

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  • ...Several modulators targeting the audio range have been reported recently, where power reduction is the main motivation for choosing CTDSMs over their discrete-time counterparts [1]–[6]....

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  • ...Thanks to this approach, we are able to achieve 15 bit performance in single bit CTDSMs based on NRZ and SCR feedback DACs with power dissipation that is comparable to that of the multibit modulator we reported in [6]....

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Journal ArticleDOI
TL;DR: An inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators is proposed and the prototype DeltaSigma modulators achieved high power efficiency maintaining sufficient performances for practical applications.
Abstract: An operational transconductance amplifier (OTA) is a major building block and consumes most of the power in switched-capacitor (SC) circuits, but it is difficult to design low-voltage OTAs in scaled CMOS technologies. Instead of using an OTA, this paper proposes an inverter-based SC circuit and its application to low-voltage, low-power delta-sigma (DeltaSigma) modulators. Detailed analysis and design optimizations are also provided. Three inverter-based DeltaSigma modulators are implemented for an implantable pacemaker, a CMOS image sensor, and an audio codec. The modulator-I for an implantable pacemaker achieves 65-dB peak-SNDR for 120-Hz bandwidth consuming 0.73 muW with 1.5 V supply. The modulator-II for a CMOS image sensor implemented with 320-channel parallel ADC architecture achieves 63-dB peak-SNDR for 8-kHz bandwidth consuming 5.6 muW for each channel with 1.2-V supply. The modulator-III for an audio codec achieves 81-dB peak-SNDR with 20-kHz bandwidth consuming 36 muW with 0.7-V supply. The prototype DeltaSigma modulators achieved high power efficiency maintaining sufficient performances for practical applications.

268 citations

Journal ArticleDOI
TL;DR: In this paper, a single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented, which is intended to minimize the power consumption in a lowvoltage environment.
Abstract: A single-loop third-order switched-capacitor /spl Sigma/-/spl Delta/ modulator in 90-nm standard digital CMOS technology is presented. The design is intended to minimize the power consumption in a low-voltage environment. A load-compensated OTA with rail-to-rail output swing and gain enhancement is chosen in this design, which provides higher power efficiency than the two-stage OTA. To lower the power consumption further, class-AB operation is also adapted in the OTA design. Due to the relatively low threshold voltage of the advanced technology, no clock bootstrapping circuits are needed to drive the switches and the power consumption of the digital circuits is reduced. All the capacitors are implemented using multilayer metal-wall structure, which can provide high-density capacitance. The modulator achieves 88-dB dynamic range in 20-kHz signal bandwidth with an oversampling ratio of 100. The power consumption is 140 /spl mu/W under 1-V supply voltage and the chip core size is 0.18 mm/sup 2/.

209 citations

Journal ArticleDOI
TL;DR: In this paper, the effect of clock jitter on the dynamic range of discrete-time (DT) and continuous-time sigma-delta modulators is addressed, and it is shown that clock jitters in DT modulators mix with the input signal, while for CT modulators, the jitter mixes with the out-ofband quantization error and elevates the passband noise.
Abstract: The effect of clock jitter on the dynamic range of discrete-time (DT) and continuous-time (CT) sigma-delta modulators is addressed. It is shown that clock jitter in DT modulators mixes with the input signal, while for CT modulators, the jitter mixes with the out-of-band quantization error and elevates the passband noise. The signal-to-noise ratio of CT modulators is shown to be more susceptible to clock jitter than their DT counterparts. Analytical and simulation results are provided.

164 citations


"Power Reduction in Continuous-Time ..." refers methods in this paper

  • ...For the modulator with the NRZ DAC, if , it can be shown (by proceeding along the lines of [11]) that the RMS in-band noise due to sinusoidal jitter is white and has an RMS value given by...

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