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Power semiconductor devices and methods of manufacture

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TLDR
In this article, a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance.
Abstract
Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented. According to another aspect of the invention, charge balanced power devices incorporate temperature and current sensing elements such as diodes on the same die. Other aspects of the invention improve equivalent series resistance (ESR) for power devices, incorporate additional circuitry on the same chip as the power device and provide improvements to the packaging of charge balanced power devices.

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Citations
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References
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Journal ArticleDOI

Theory of Semiconductor Superjunction Devices

TL;DR: In this article, a new theory of semiconductor devices, called "semiconductor superjunction (SJ) theory", is presented, which utilizes a number of alternately stacked, p-and n-type, heavily doped, thin semiconductor layers.
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TL;DR: In this paper, a gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell, and a buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode.
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Semiconductor power devices with alternating conductivity type high-voltage breakdown regions

TL;DR: In this article, the CB-layer was introduced, where two kinds of semiconductor regions with opposite types of conduction are alternatively arranged, viewed from any cross-section parallel to the interface between the layer itself and the n + (or p + )-region.
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Modeling and simulation of power electronic converters

TL;DR: The major focus of the paper is on averaged models of various kinds, but sampled-data models are also introduced and the importance of hierarchical modeling and simulation is emphasized.