Power Testing of an FPGA based System Using Modelsim Code Coverage capability
Khalil Arshak,E. Jafer,Christian Ibala +2 more
- pp 1-4
Reads0
Chats0
TLDR
The power performance of the FPGA based design will be investigated using XILINX Xpower tool using Modelsim Code coverage feature has been incorporated to make sure that the test-bench cover all the nets branch statement of the design and create the most accurate Value Change Dump (VCD) file for the power consumption estimation.Abstract:
Field programmable gate arrays (FPGAs) play many important roles, ranging from small glue logic replacement to System-on-Chip designs. Nevertheless, FPGA vendors can not accurately specify the energy consumption information of their products on the device data sheets because the energy consumption of FPGAs is strongly dependent on target circuit including resource utilization, logic partitioning, mapping, placement and route. While major CAD tools have started to report average power consumption under given transition activities, energy optimal FPGA design demands more detailed energy estimation. The target design is telemetry system used for health monitoring applications. The FPGA is acting as the controller unit of both transmitter and receiver. Transmitter side is reading data from interfaced sensors. Verilog-HDL has been used to implement the required functions of the FPGA. In this paper, the power performance of the FPGA based design will be investigated using XILINX Xpower tool. Modelsim Code coverage feature has been incorporated to make sure that the test-bench cover all the nets branch statement of the design and create the most accurate Value Change Dump (VCD) file for the power consumption estimation.read more
Citations
More filters
Journal ArticleDOI
FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm
TL;DR: The results show that the proposed schemes are able to reduce the logic and signal power by 60% and 27%, respectively on a Virtex 2 Pro FPGA while maintaining a high level of throughput.
Proceedings ArticleDOI
A Survey on System-Level Techniques for Power Reduction in Field Programmable Gate Array (FPGA)-Based Devices
Paweł Czapski,Andrzej Sluzek +1 more
TL;DR: This paper addresses means of the dynamic power consumption reduction on the system-level and envisaged that proposed techniques may allow achieving substantial power consumption savings with negligible hardware overheads while maintaining the energy per operation.
Proceedings ArticleDOI
A functional coverage approach for direct testing: An industrial IP as a case study
Sameh El-Ashry,Khaled Salah +1 more
TL;DR: This paper proposes an automated functional coverage method that is proposed to be used along with direct testing in order to automatically track the progress of the test-plan and may predict uncovered corner cases scenarios.
References
More filters
Journal ArticleDOI
Leakage current: Moore's law meets static power
Nam Sung Kim,Todd Austin,D. Baauw,Trevor Mudge,Krisztian Flautner,Jie Hu,Mary Jane Irwin,Mahmut Kandemir,Vijaykrishnan Narayanan +8 more
TL;DR: The other source of power dissipation in microprocessors, dynamic power, arises from the repeated capacitance charge and discharge on the output of the hundreds of millions of gates in today's chips.
Book
Low Power Design Methodologies
Jan M. Rabaey,Massoud Pedram +1 more
TL;DR: The present work focuses on the design of low power circuit technologies for portable video-on-demand in wireless communication using CMOS, and the development of algorithms and architectural level methodologies for this purpose.
Proceedings ArticleDOI
Dynamic power consumption in Virtex™-II FPGA family
TL;DR: The dynamic power consumption in the fabric of Field Programmable Gate Arrays (FPGAs) is analyzed by taking advantage of both simulation and measurement, and it is concluded that dynamic power dissipation of a Virtex-II CLB is 5.9μW per MHz for typical designs, but it may vary significantly depending on the switching activity.
Proceedings ArticleDOI
Low-power high-level synthesis for FPGA architectures
TL;DR: A low power high level synthesis system, named LOPASS, for FPGA designs that includes a simulated annealing engine that carries out resource selection, function unit binding, scheduling, register binding, and data path generation simultaneously to effectively reduce power.
Power estimation for field programmable gate arrays
TL;DR: This book describes the development and use of DNA testing for the detection of infectious diseases and some of the techniques used to identify these diseases are cytogenetically modified.